Searched hist:"37 c0ffaad21401eacc6618a121cc2c501131026f" (Results 1 – 6 of 6) sorted by relevance
| /linux/drivers/net/ethernet/altera/ |
| H A D | altera_msgdma.h | diff 37c0ffaad21401eacc6618a121cc2c501131026f Thu Apr 24 23:58:08 CEST 2014 Vince Bridgers <vbridger@altera.com> Altera TSE: Work around unaligned DMA receive packet issue with Altera SGDMA
This patch works around a recently discovered unaligned receive dma problem
with the Altera SGMDA. The Altera SGDMA component cannot be configured to
DMA data to unaligned addresses for receive packet operations from the
Triple Speed Ethernet component because of a potential data transfer
corruption that can occur. This patch addresses this issue by
utilizing the shift 16 bits feature of the Altera Triple Speed Ethernet
component and modifying the receive buffer physical addresses accordingly
such that the target receive DMA address is always aligned on a 32-bit
boundary.
Signed-off-by: Vince Bridgers <vbridgers2013@gmail.com>
Tested-by: Matthew Gerlach <mgerlach@altera.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
|
| H A D | altera_sgdma.h | diff 37c0ffaad21401eacc6618a121cc2c501131026f Thu Apr 24 23:58:08 CEST 2014 Vince Bridgers <vbridger@altera.com> Altera TSE: Work around unaligned DMA receive packet issue with Altera SGDMA
This patch works around a recently discovered unaligned receive dma problem
with the Altera SGMDA. The Altera SGDMA component cannot be configured to
DMA data to unaligned addresses for receive packet operations from the
Triple Speed Ethernet component because of a potential data transfer
corruption that can occur. This patch addresses this issue by
utilizing the shift 16 bits feature of the Altera Triple Speed Ethernet
component and modifying the receive buffer physical addresses accordingly
such that the target receive DMA address is always aligned on a 32-bit
boundary.
Signed-off-by: Vince Bridgers <vbridgers2013@gmail.com>
Tested-by: Matthew Gerlach <mgerlach@altera.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
|
| H A D | altera_msgdma.c | diff 37c0ffaad21401eacc6618a121cc2c501131026f Thu Apr 24 23:58:08 CEST 2014 Vince Bridgers <vbridger@altera.com> Altera TSE: Work around unaligned DMA receive packet issue with Altera SGDMA
This patch works around a recently discovered unaligned receive dma problem
with the Altera SGMDA. The Altera SGDMA component cannot be configured to
DMA data to unaligned addresses for receive packet operations from the
Triple Speed Ethernet component because of a potential data transfer
corruption that can occur. This patch addresses this issue by
utilizing the shift 16 bits feature of the Altera Triple Speed Ethernet
component and modifying the receive buffer physical addresses accordingly
such that the target receive DMA address is always aligned on a 32-bit
boundary.
Signed-off-by: Vince Bridgers <vbridgers2013@gmail.com>
Tested-by: Matthew Gerlach <mgerlach@altera.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
|
| H A D | altera_sgdma.c | diff 37c0ffaad21401eacc6618a121cc2c501131026f Thu Apr 24 23:58:08 CEST 2014 Vince Bridgers <vbridger@altera.com> Altera TSE: Work around unaligned DMA receive packet issue with Altera SGDMA
This patch works around a recently discovered unaligned receive dma problem
with the Altera SGMDA. The Altera SGDMA component cannot be configured to
DMA data to unaligned addresses for receive packet operations from the
Triple Speed Ethernet component because of a potential data transfer
corruption that can occur. This patch addresses this issue by
utilizing the shift 16 bits feature of the Altera Triple Speed Ethernet
component and modifying the receive buffer physical addresses accordingly
such that the target receive DMA address is always aligned on a 32-bit
boundary.
Signed-off-by: Vince Bridgers <vbridgers2013@gmail.com>
Tested-by: Matthew Gerlach <mgerlach@altera.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
|
| H A D | altera_tse.h | diff 37c0ffaad21401eacc6618a121cc2c501131026f Thu Apr 24 23:58:08 CEST 2014 Vince Bridgers <vbridger@altera.com> Altera TSE: Work around unaligned DMA receive packet issue with Altera SGDMA
This patch works around a recently discovered unaligned receive dma problem
with the Altera SGMDA. The Altera SGDMA component cannot be configured to
DMA data to unaligned addresses for receive packet operations from the
Triple Speed Ethernet component because of a potential data transfer
corruption that can occur. This patch addresses this issue by
utilizing the shift 16 bits feature of the Altera Triple Speed Ethernet
component and modifying the receive buffer physical addresses accordingly
such that the target receive DMA address is always aligned on a 32-bit
boundary.
Signed-off-by: Vince Bridgers <vbridgers2013@gmail.com>
Tested-by: Matthew Gerlach <mgerlach@altera.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
|
| H A D | altera_tse_main.c | diff 37c0ffaad21401eacc6618a121cc2c501131026f Thu Apr 24 23:58:08 CEST 2014 Vince Bridgers <vbridger@altera.com> Altera TSE: Work around unaligned DMA receive packet issue with Altera SGDMA
This patch works around a recently discovered unaligned receive dma problem
with the Altera SGMDA. The Altera SGDMA component cannot be configured to
DMA data to unaligned addresses for receive packet operations from the
Triple Speed Ethernet component because of a potential data transfer
corruption that can occur. This patch addresses this issue by
utilizing the shift 16 bits feature of the Altera Triple Speed Ethernet
component and modifying the receive buffer physical addresses accordingly
such that the target receive DMA address is always aligned on a 32-bit
boundary.
Signed-off-by: Vince Bridgers <vbridgers2013@gmail.com>
Tested-by: Matthew Gerlach <mgerlach@altera.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
|