Searched hist:"34 e3c4500cdc06094b37a41b622598098308ba8f" (Results 1 – 6 of 6) sorted by relevance
| /linux/arch/loongarch/include/uapi/asm/ |
| H A D | hwcap.h | diff 34e3c4500cdc06094b37a41b622598098308ba8f Tue Sep 24 09:32:20 CEST 2024 Jiaxun Yang <jiaxun.yang@flygoat.com> LoongArch: Rework CPU feature probe from CPUCFG/IOCSR
Probe ISA level, TLB, IOCSR information from CPUCFG to improve kernel
resilience to different core implementations.
BTW, IOCSR register definition appears to be a platform-specific spec
instead of an architecture spec, even for the Loongson CPUs there is no
guarantee that IOCSR will always present.
Thus it's dangerous to perform IOCSR probing without checking CPU type
and instruction availability.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
|
| /linux/arch/loongarch/include/asm/ |
| H A D | cpu-features.h | diff 34e3c4500cdc06094b37a41b622598098308ba8f Tue Sep 24 09:32:20 CEST 2024 Jiaxun Yang <jiaxun.yang@flygoat.com> LoongArch: Rework CPU feature probe from CPUCFG/IOCSR
Probe ISA level, TLB, IOCSR information from CPUCFG to improve kernel
resilience to different core implementations.
BTW, IOCSR register definition appears to be a platform-specific spec
instead of an architecture spec, even for the Loongson CPUs there is no
guarantee that IOCSR will always present.
Thus it's dangerous to perform IOCSR probing without checking CPU type
and instruction availability.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
|
| H A D | cpu.h | diff 34e3c4500cdc06094b37a41b622598098308ba8f Tue Sep 24 09:32:20 CEST 2024 Jiaxun Yang <jiaxun.yang@flygoat.com> LoongArch: Rework CPU feature probe from CPUCFG/IOCSR
Probe ISA level, TLB, IOCSR information from CPUCFG to improve kernel
resilience to different core implementations.
BTW, IOCSR register definition appears to be a platform-specific spec
instead of an architecture spec, even for the Loongson CPUs there is no
guarantee that IOCSR will always present.
Thus it's dangerous to perform IOCSR probing without checking CPU type
and instruction availability.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
|
| H A D | loongarch.h | diff 34e3c4500cdc06094b37a41b622598098308ba8f Tue Sep 24 09:32:20 CEST 2024 Jiaxun Yang <jiaxun.yang@flygoat.com> LoongArch: Rework CPU feature probe from CPUCFG/IOCSR
Probe ISA level, TLB, IOCSR information from CPUCFG to improve kernel
resilience to different core implementations.
BTW, IOCSR register definition appears to be a platform-specific spec
instead of an architecture spec, even for the Loongson CPUs there is no
guarantee that IOCSR will always present.
Thus it's dangerous to perform IOCSR probing without checking CPU type
and instruction availability.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
|
| /linux/arch/loongarch/kernel/ |
| H A D | proc.c | diff 34e3c4500cdc06094b37a41b622598098308ba8f Tue Sep 24 09:32:20 CEST 2024 Jiaxun Yang <jiaxun.yang@flygoat.com> LoongArch: Rework CPU feature probe from CPUCFG/IOCSR
Probe ISA level, TLB, IOCSR information from CPUCFG to improve kernel
resilience to different core implementations.
BTW, IOCSR register definition appears to be a platform-specific spec
instead of an architecture spec, even for the Loongson CPUs there is no
guarantee that IOCSR will always present.
Thus it's dangerous to perform IOCSR probing without checking CPU type
and instruction availability.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
|
| H A D | cpu-probe.c | diff 34e3c4500cdc06094b37a41b622598098308ba8f Tue Sep 24 09:32:20 CEST 2024 Jiaxun Yang <jiaxun.yang@flygoat.com> LoongArch: Rework CPU feature probe from CPUCFG/IOCSR
Probe ISA level, TLB, IOCSR information from CPUCFG to improve kernel
resilience to different core implementations.
BTW, IOCSR register definition appears to be a platform-specific spec
instead of an architecture spec, even for the Loongson CPUs there is no
guarantee that IOCSR will always present.
Thus it's dangerous to perform IOCSR probing without checking CPU type
and instruction availability.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
|