Searched hist:"2 b2dbc2f94e55c940e1eed70706f363aa94373b0" (Results 1 – 2 of 2) sorted by relevance
| /linux/drivers/clk/tegra/ |
| H A D | cvb.h | diff 2b2dbc2f94e55c940e1eed70706f363aa94373b0 Fri Jan 04 04:06:51 CET 2019 Joseph Lo <josephl@nvidia.com> clk: tegra: dfll: add CVB tables for Tegra210
Add CVB tables with different chip characterization, so that we can
generate the customize OPP table that suitable for different chips with
different SKUs.
The parameter 'tune_high_min_millivolts' is first time introduced in
this patch, which didn't use in the DFLL driver for clock and voltage
tuning before. It will be used later when DFLL in high voltage range.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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| H A D | clk-tegra124-dfll-fcpu.c | diff 2b2dbc2f94e55c940e1eed70706f363aa94373b0 Fri Jan 04 04:06:51 CET 2019 Joseph Lo <josephl@nvidia.com> clk: tegra: dfll: add CVB tables for Tegra210
Add CVB tables with different chip characterization, so that we can
generate the customize OPP table that suitable for different chips with
different SKUs.
The parameter 'tune_high_min_millivolts' is first time introduced in
this patch, which didn't use in the DFLL driver for clock and voltage
tuning before. It will be used later when DFLL in high voltage range.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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