Searched hist:"289 f40c67b7239b8cd16b278ff5fef126483b75e" (Results 1 – 2 of 2) sorted by relevance
| /freebsd/sys/amd64/amd64/ |
| H A D | vm_machdep.c | diff 289f40c67b7239b8cd16b278ff5fef126483b75e Thu Sep 11 20:33:57 CEST 2008 John Baldwin <jhb@FreeBSD.org> Update the comments above the 0xcf9 register reset attempt to match the
code. We only attempt a single reset using this method (a "hard" reset),
and we use two writes to ensure there is a 0 -> 1 transition in bit 2 to
force a reset.
MFC after: 1 week
diff 289f40c67b7239b8cd16b278ff5fef126483b75e Thu Sep 11 20:33:57 CEST 2008 John Baldwin <jhb@FreeBSD.org> Update the comments above the 0xcf9 register reset attempt to match the
code. We only attempt a single reset using this method (a "hard" reset),
and we use two writes to ensure there is a 0 -> 1 transition in bit 2 to
force a reset.
MFC after: 1 week
|
| /freebsd/sys/i386/i386/ |
| H A D | vm_machdep.c | diff 289f40c67b7239b8cd16b278ff5fef126483b75e Thu Sep 11 20:33:57 CEST 2008 John Baldwin <jhb@FreeBSD.org> Update the comments above the 0xcf9 register reset attempt to match the
code. We only attempt a single reset using this method (a "hard" reset),
and we use two writes to ensure there is a 0 -> 1 transition in bit 2 to
force a reset.
MFC after: 1 week
diff 289f40c67b7239b8cd16b278ff5fef126483b75e Thu Sep 11 20:33:57 CEST 2008 John Baldwin <jhb@FreeBSD.org> Update the comments above the 0xcf9 register reset attempt to match the
code. We only attempt a single reset using this method (a "hard" reset),
and we use two writes to ensure there is a 0 -> 1 transition in bit 2 to
force a reset.
MFC after: 1 week
|