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H A Dsifive-prci.hdiff 263ac3908516abb0392747bbf595af2b13df5fa2 Wed Dec 09 10:49:15 CET 2020 Zong Li <zong.li@sifive.com> clk: sifive: Fix the wrong bit field shift

The clk enable bit should be 31 instead of 24.

Signed-off-by: Zong Li <zong.li@sifive.com>
Reported-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Link: https://lore.kernel.org/r/20201209094916.17383-5-zong.li@sifive.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>