Searched hist:"24 ee38ffe61a68fc35065fcab1908883a34c866b" (Results 1 – 2 of 2) sorted by relevance
| /linux/arch/x86/events/intel/ |
| H A D | ds.c | diff 24ee38ffe61a68fc35065fcab1908883a34c866b Mon Apr 12 16:30:49 CEST 2021 Kan Liang <kan.liang@linux.intel.com> perf/x86: Hybrid PMU support for event constraints
The events are different among hybrid PMUs. Each hybrid PMU should use
its own event constraints.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Andi Kleen <ak@linux.intel.com>
Link: https://lkml.kernel.org/r/1618237865-33448-10-git-send-email-kan.liang@linux.intel.com
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| /linux/arch/x86/events/ |
| H A D | perf_event.h | diff 24ee38ffe61a68fc35065fcab1908883a34c866b Mon Apr 12 16:30:49 CEST 2021 Kan Liang <kan.liang@linux.intel.com> perf/x86: Hybrid PMU support for event constraints
The events are different among hybrid PMUs. Each hybrid PMU should use
its own event constraints.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Andi Kleen <ak@linux.intel.com>
Link: https://lkml.kernel.org/r/1618237865-33448-10-git-send-email-kan.liang@linux.intel.com
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