Searched hist:"242 b1d713386e8e2fd7f62cc1ed4681a12290848" (Results 1 – 5 of 5) sorted by relevance
| /linux/drivers/memory/tegra/ |
| H A D | Makefile | diff 242b1d713386e8e2fd7f62cc1ed4681a12290848 Fri Nov 07 16:10:41 CET 2014 Thierry Reding <treding@nvidia.com> memory: tegra: Add Tegra132 support
The memory controller on Tegra132 is very similar to the one found on
Tegra124. But the Denver CPUs don't have an outer cache, so dcache
maintenance is done slightly differently.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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| H A D | mc.h | diff 242b1d713386e8e2fd7f62cc1ed4681a12290848 Fri Nov 07 16:10:41 CET 2014 Thierry Reding <treding@nvidia.com> memory: tegra: Add Tegra132 support
The memory controller on Tegra132 is very similar to the one found on
Tegra124. But the Denver CPUs don't have an outer cache, so dcache
maintenance is done slightly differently.
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
| H A D | tegra124.c | diff 242b1d713386e8e2fd7f62cc1ed4681a12290848 Fri Nov 07 16:10:41 CET 2014 Thierry Reding <treding@nvidia.com> memory: tegra: Add Tegra132 support
The memory controller on Tegra132 is very similar to the one found on
Tegra124. But the Denver CPUs don't have an outer cache, so dcache
maintenance is done slightly differently.
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
| H A D | mc.c | diff 242b1d713386e8e2fd7f62cc1ed4681a12290848 Fri Nov 07 16:10:41 CET 2014 Thierry Reding <treding@nvidia.com> memory: tegra: Add Tegra132 support
The memory controller on Tegra132 is very similar to the one found on
Tegra124. But the Denver CPUs don't have an outer cache, so dcache
maintenance is done slightly differently.
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
| /linux/drivers/iommu/ |
| H A D | Kconfig | diff 242b1d713386e8e2fd7f62cc1ed4681a12290848 Fri Nov 07 16:10:41 CET 2014 Thierry Reding <treding@nvidia.com> memory: tegra: Add Tegra132 support
The memory controller on Tegra132 is very similar to the one found on
Tegra124. But the Denver CPUs don't have an outer cache, so dcache
maintenance is done slightly differently.
Signed-off-by: Thierry Reding <treding@nvidia.com>
|