Searched hist:"1639406 a31c23ca07a2b8a9b45d1c400debda9e9" (Results 1 – 2 of 2) sorted by relevance
| /linux/drivers/gpu/drm/i915/display/ |
| H A D | intel_dp_link_training.c | diff 1639406a31c23ca07a2b8a9b45d1c400debda9e9 Sat Jan 23 00:26:42 CET 2021 Manasi Navare <manasi.d.navare@intel.com> drm/i915/display/vrr: Set IGNORE_MSA_PAR state in DP Sink
If VRR is enabled, the sink should ignore MSA parameters
and regenerate incoming video stream without depending
on these parameters. Hence set the MSA_TIMING_PAR_IGNORE_EN
bit if VRR is enabled.
Reset this bit on VRR disable.
v2:
* ACtually set the dpcd msa ignore bit (Ville)
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210122232647.22688-13-manasi.d.navare@intel.com
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| H A D | intel_ddi.c | diff 1639406a31c23ca07a2b8a9b45d1c400debda9e9 Sat Jan 23 00:26:42 CET 2021 Manasi Navare <manasi.d.navare@intel.com> drm/i915/display/vrr: Set IGNORE_MSA_PAR state in DP Sink
If VRR is enabled, the sink should ignore MSA parameters
and regenerate incoming video stream without depending
on these parameters. Hence set the MSA_TIMING_PAR_IGNORE_EN
bit if VRR is enabled.
Reset this bit on VRR disable.
v2:
* ACtually set the dpcd msa ignore bit (Ville)
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210122232647.22688-13-manasi.d.navare@intel.com
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