Searched hist:"159 fd7b8d3d12b27593d4fe3f6ae1d8e14ea9d0b" (Results 1 – 2 of 2) sorted by relevance
| /linux/arch/arm64/kernel/ |
| H A D | entry-fpsimd.S | diff 159fd7b8d3d12b27593d4fe3f6ae1d8e14ea9d0b Mon May 14 19:51:09 CEST 2018 Dave Martin <Dave.Martin@arm.com> arm64/sve: Write ZCR_EL1 on context switch only if changed
Writes to ZCR_EL1 are self-synchronising, and so may be expensive
in typical implementations.
This patch adopts the approach used for costly system register
writes elsewhere in the kernel: the system register write is
suppressed if it would not change the stored value.
Since the common case will be that of switching between tasks that
use the same vector length as one another, prediction hit rates on
the conditional branch should be reasonably good, with lower
expected amortised cost than the unconditional execution of a
heavyweight self-synchronising instruction.
Signed-off-by: Dave Martin <Dave.Martin@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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| /linux/arch/arm64/include/asm/ |
| H A D | fpsimdmacros.h | diff 159fd7b8d3d12b27593d4fe3f6ae1d8e14ea9d0b Mon May 14 19:51:09 CEST 2018 Dave Martin <Dave.Martin@arm.com> arm64/sve: Write ZCR_EL1 on context switch only if changed
Writes to ZCR_EL1 are self-synchronising, and so may be expensive
in typical implementations.
This patch adopts the approach used for costly system register
writes elsewhere in the kernel: the system register write is
suppressed if it would not change the stored value.
Since the common case will be that of switching between tasks that
use the same vector length as one another, prediction hit rates on
the conditional branch should be reasonably good, with lower
expected amortised cost than the unconditional execution of a
heavyweight self-synchronising instruction.
Signed-off-by: Dave Martin <Dave.Martin@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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