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| /linux/Documentation/devicetree/bindings/clock/ |
| H A D | nvidia,tegra124-dfll.txt | 0c59d26770333cf605d9119a78dd6c1ebebc6a61 Wed May 13 16:58:35 CEST 2015 Tuomas Tynkkynen <ttynkkynen@nvidia.com> clk: tegra: Add binding for the Tegra124 DFLL clocksource
The DFLL is the main clocksource for the fast CPU cluster on Tegra124
and also provides automatic CPU rail voltage scaling as well. The DFLL
is a separate IP block from the usual Tegra124 clock-and-reset
controller, so it gets its own node in the device tree.
Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi>
Acked-by: Michael Turquette <mturquette@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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