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| H A D | phy-cadence-sierra.c | diff 09d976b3e8e257ff44405b6506bbaae6be1a6b3c Thu Dec 23 07:01:37 CET 2021 Swapnil Jakhade <sjakhade@cadence.com> phy: cadence: Sierra: Add support for derived reference clock output
Sierra has derived differential reference clock output which is sourced
after the spread spectrum generation has been added. Add support to drive
derived reference clock out of serdes. Model this derived clock as a
"clock" so that platforms using this can enable it.
Sierra Main LC VCO PLL divider 1 clock is programmed to output 100MHz
clock output.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Reviewed-by: Aswath Govindraju <a-govindraju@ti.com>
Link: https://lore.kernel.org/r/20211223060137.9252-16-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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