Searched hist:"0865805 d82d4c822647ee35ab2629c48cc40706b" (Results 1 – 4 of 4) sorted by relevance
| /linux/drivers/clk/at91/ |
| H A D | clk-audio-pll.c | 0865805d82d4c822647ee35ab2629c48cc40706b Thu Aug 10 08:34:03 CEST 2017 Quentin Schulz <quentin.schulz@free-electrons.com> clk: at91: add audio pll clock drivers
This new clock driver set allows to have a fractional divided clock that
would generate a precise clock particularly suitable for audio
applications.
The main audio pll clock has two children clocks: one that is connected
to the PMC, the other that can directly drive a pad. As these two routes
have different enable bits and different dividers and divider formulas,
they are handled by two different drivers. Each of them could modify the
rate of the main audio pll parent.
The main audio pll clock can output 620MHz to 700MHz.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
| H A D | Makefile | diff 0865805d82d4c822647ee35ab2629c48cc40706b Thu Aug 10 08:34:03 CEST 2017 Quentin Schulz <quentin.schulz@free-electrons.com> clk: at91: add audio pll clock drivers
This new clock driver set allows to have a fractional divided clock that
would generate a precise clock particularly suitable for audio
applications.
The main audio pll clock has two children clocks: one that is connected
to the PMC, the other that can directly drive a pad. As these two routes
have different enable bits and different dividers and divider formulas,
they are handled by two different drivers. Each of them could modify the
rate of the main audio pll parent.
The main audio pll clock can output 620MHz to 700MHz.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
| /linux/include/linux/clk/ |
| H A D | at91_pmc.h | diff 0865805d82d4c822647ee35ab2629c48cc40706b Thu Aug 10 08:34:03 CEST 2017 Quentin Schulz <quentin.schulz@free-electrons.com> clk: at91: add audio pll clock drivers
This new clock driver set allows to have a fractional divided clock that
would generate a precise clock particularly suitable for audio
applications.
The main audio pll clock has two children clocks: one that is connected
to the PMC, the other that can directly drive a pad. As these two routes
have different enable bits and different dividers and divider formulas,
they are handled by two different drivers. Each of them could modify the
rate of the main audio pll parent.
The main audio pll clock can output 620MHz to 700MHz.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
| /linux/arch/arm/mach-at91/ |
| H A D | Kconfig | diff 0865805d82d4c822647ee35ab2629c48cc40706b Thu Aug 10 08:34:03 CEST 2017 Quentin Schulz <quentin.schulz@free-electrons.com> clk: at91: add audio pll clock drivers
This new clock driver set allows to have a fractional divided clock that
would generate a precise clock particularly suitable for audio
applications.
The main audio pll clock has two children clocks: one that is connected
to the PMC, the other that can directly drive a pad. As these two routes
have different enable bits and different dividers and divider formulas,
they are handled by two different drivers. Each of them could modify the
rate of the main audio pll parent.
The main audio pll clock can output 620MHz to 700MHz.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|