Searched hist:"02599 bc7f7047f2b316ab499f41d72ca14e3b3d3" (Results 1 – 3 of 3) sorted by relevance
/linux/drivers/gpu/drm/amd/amdgpu/ |
H A D | mxgpu_vi.c | diff 02599bc7f7047f2b316ab499f41d72ca14e3b3d3 Mon Dec 20 23:27:37 CET 2021 Andrey Grodzovsky <andrey.grodzovsky@amd.com> drm/amd/virt: For SRIOV send GPU reset directly to TDR queue.
No need to to trigger another work queue inside the work queue.
v3:
Problem: Extra reset caused by host side FLR notification following guest side triggered reset. Fix: Preven qeuing flr_work from mailbox irq if guest already executing a reset.
Suggested-by: Liu Shaoyun <Shaoyun.Liu@amd.com> Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Liu Shaoyun <Shaoyun.Liu@amd.com> Link: https://www.spinics.net/lists/amd-gfx/msg74114.html
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H A D | mxgpu_nv.c | diff 02599bc7f7047f2b316ab499f41d72ca14e3b3d3 Mon Dec 20 23:27:37 CET 2021 Andrey Grodzovsky <andrey.grodzovsky@amd.com> drm/amd/virt: For SRIOV send GPU reset directly to TDR queue.
No need to to trigger another work queue inside the work queue.
v3:
Problem: Extra reset caused by host side FLR notification following guest side triggered reset. Fix: Preven qeuing flr_work from mailbox irq if guest already executing a reset.
Suggested-by: Liu Shaoyun <Shaoyun.Liu@amd.com> Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Liu Shaoyun <Shaoyun.Liu@amd.com> Link: https://www.spinics.net/lists/amd-gfx/msg74114.html
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H A D | mxgpu_ai.c | diff 02599bc7f7047f2b316ab499f41d72ca14e3b3d3 Mon Dec 20 23:27:37 CET 2021 Andrey Grodzovsky <andrey.grodzovsky@amd.com> drm/amd/virt: For SRIOV send GPU reset directly to TDR queue.
No need to to trigger another work queue inside the work queue.
v3:
Problem: Extra reset caused by host side FLR notification following guest side triggered reset. Fix: Preven qeuing flr_work from mailbox irq if guest already executing a reset.
Suggested-by: Liu Shaoyun <Shaoyun.Liu@amd.com> Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Liu Shaoyun <Shaoyun.Liu@amd.com> Link: https://www.spinics.net/lists/amd-gfx/msg74114.html
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