Searched +full:zynqmp +full:- +full:gpio +full:- +full:modepin (Results 1 – 4 of 4) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/gpio/xlnx,zynqmp-gpio-modepin.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: ZynqMP Mode Pin GPIO controller10 PS_MODE is 4-bits boot mode pins sampled on POR deassertion. Mode Pin11 GPIO controller with configurable from numbers of pins (from 0 to 3 per15 - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>19 const: xlnx,zynqmp-gpio-modepin21 gpio-controller: true[all …]
1 // SPDX-License-Identifier: GPL-2.03 * Driver for the ps-mode pin configuration.10 #include <linux/gpio/driver.h>16 #include <linux/firmware/xlnx-zynqmp.h>18 /* 4-bit boot mode pins */22 * modepin_gpio_get_value - Get the state of the specified pin of GPIO device24 * @pin: gpio pin number within the device26 * This function reads the state of the specified pin of the GPIO device.28 * Return: 0 if the pin is low, 1 if pin is high, -EINVAL wrong pin configured50 * modepin_gpio_set_value - Modify the state of the pin with specified value[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Nava kishore Manne <nava.kishore.manne@amd.com>12 description: The zynqmp-firmware node describes the interface to platform13 firmware. ZynqMP has an interface to communicate with secure firmware.23 - description: For implementations complying for Zynq Ultrascale+ MPSoC.24 const: xlnx,zynqmp-firmware26 - description: For implementations complying for Versal.[all …]
1 // SPDX-License-Identifier: GPL-2.03 * dwc3-xilinx.c - Xilinx DWC3 controller specific glue driver15 #include <linux/dma-mapping.h>16 #include <linux/gpio/consumer.h>22 #include <linux/firmware/xlnx-zynqmp.h>62 reg = readl(priv_data->regs + XLNX_USB_PHY_RST_EN); in dwc3_xlnx_mask_phy_rst()69 writel(reg, priv_data->regs + XLNX_USB_PHY_RST_EN); in dwc3_xlnx_mask_phy_rst()74 struct device *dev = priv_data->dev; in dwc3_xlnx_set_coherency()82 if (of_dma_is_coherent(dev->of_node) || device_iommu_mapped(dev)) { in dwc3_xlnx_set_coherency()83 reg = readl(priv_data->regs + coherency_offset); in dwc3_xlnx_set_coherency()[all …]