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Searched +full:zynqmp +full:- +full:firmware (Results 1 – 21 of 21) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/firmware/xilinx/
H A Dxlnx,zynqmp-firmware.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx firmware driver
10 - Nava kishore Manne <nava.kishore.manne@amd.com>
12 description: The zynqmp-firmware node describes the interface to platform
13 firmware. ZynqMP has an interface to communicate with secure firmware.
14 Firmware driver provides an interface to firmware APIs. Interface APIs
23 - description: For implementations complying for Zynq Ultrascale+ MPSoC.
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H A Dxlnx,zynqmp-firmware.txt1 -----------------------------------------------------------------
2 Device Tree Bindings for the Xilinx Zynq MPSoC Firmware Interface
3 -----------------------------------------------------------------
5 The zynqmp-firmware node describes the interface to platform firmware.
6 ZynqMP has an interface to communicate with secure firmware. Firmware
7 driver provides an interface to firmware APIs. Interface APIs can be
14 - compatible: Must contain any of below:
15 "xlnx,zynqmp-firmware" for Zynq Ultrascale+ MPSoC
16 "xlnx,versal-firmware" for Versal
17 - method: The method of calling the PM-API firmware layer.
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/freebsd/sys/contrib/device-tree/Bindings/power/reset/
H A Dxlnx,zynqmp-power.txt1 --------------------------------------------------------------------
3 --------------------------------------------------------------------
4 The zynqmp-power node describes the power management configurations.
8 - compatible: Must contain: "xlnx,zynqmp-power"
9 - interrupts: Interrupt specifier
12 - mbox-names : Name given to channels seen in the 'mboxes' property.
13 "tx" - Mailbox corresponding to transmit path
14 "rx" - Mailbox corresponding to receive path
15 - mboxes : Standard property to specify a Mailbox. Each value of
18 that will be the phandle to the intended sub-mailbox
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H A Dxlnx,zynqmp-power.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/reset/xlnx,zynqmp
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/freebsd/sys/contrib/device-tree/Bindings/crypto/
H A Dxlnx,zynqmp-aes.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/crypto/xlnx,zynqmp-aes.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx ZynqMP AES-GCM Hardware Accelerator
10 - Kalyani Akula <kalyani.akula@amd.com>
11 - Michal Simek <michal.simek@amd.com>
14 The ZynqMP AES-GCM hardened cryptographic accelerator is used to
19 const: xlnx,zynqmp-aes
22 - compatible
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/freebsd/sys/contrib/device-tree/Bindings/fpga/
H A Dxlnx,zynqmp-pcap-fpga.txt2 The ZynqMP SoC uses the PCAP (Processor configuration Port) to configure the
3 Programmable Logic (PL). The configuration uses the firmware interface.
6 - compatible: should contain "xlnx,zynqmp-pcap-fpga"
10 fpga-region0 {
11 compatible = "fpga-region";
12 fpga-mgr = <&zynqmp_pcap>;
13 #address-cells = <0x1>;
14 #size-cells = <0x1>;
17 firmware {
18 zynqmp_firmware: zynqmp-firmware {
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H A Dxlnx,zynqmp-pcap-fpga.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/xlnx,zynqmp-pcap-fpga.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nava kishore Manne <nava.kishore.manne@amd.com>
14 The ZynqMP SoC uses the PCAP (Processor Configuration Port) to
16 firmware interface.
20 const: xlnx,zynqmp-pcap-fpga
23 - compatible
28 - |
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/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dxlnx,zynqmp-clk.txt1 --------------------------------------------------------------------------
3 Zynq MPSoC firmware interface
4 --------------------------------------------------------------------------
12 - #clock-cells: Must be 1
13 - compatible: Must contain: "xlnx,zynqmp-clk"
14 - clocks: List of clock specifiers which are external input
18 - clock-names: List of clock names which are exteral input clocks
22 Input clocks for zynqmp Ultrascale+ clock controller:
26 - pss_ref_clk (PS reference clock)
27 - video_clk (reference clock for video system )
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H A Dxlnx,versal-clk.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/xlnx,versal-clk.yaml#
5 $schema: http://devicetree.org/meta-schema
[all...]
/freebsd/sys/contrib/device-tree/Bindings/nvmem/
H A Dxlnx,zynqmp-nvmem.txt1 --------------------------------------------------------------------------
2 = Zynq UltraScale+ MPSoC nvmem firmware driver binding =
3 --------------------------------------------------------------------------
5 like soc revision, IDCODE... etc, By using the firmware interface.
8 - compatible: should be "xlnx,zynqmp-nvmem-fw"
14 -------
16 -------
17 firmware {
18 zynqmp_firmware: zynqmp-firmware {
19 compatible = "xlnx,zynqmp-firmware";
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/freebsd/sys/contrib/device-tree/Bindings/reset/
H A Dxlnx,zynqmp-reset.txt1 --------------------------------------------------------------------------
3 --------------------------------------------------------------------------
7 about zynqmp resets.
13 - compatible: "xlnx,zynqmp-reset" for Zynq UltraScale+ MPSoC platform
14 "xlnx,versal-reset" for Versal platform
15 - #reset-cells: Specifies the number of cells needed to encode reset
18 -------
20 -------
22 firmware {
23 zynqmp_firmware: zynqmp-firmware {
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/freebsd/sys/contrib/device-tree/Bindings/power/
H A Dxlnx,zynqmp-genpd.txt1 -----------------------------------------------------------
3 -----------------------------------------------------------
4 The binding for zynqmp-power-controller follow the common
7 [1] Documentation/devicetree/bindings/power/power-domain.yaml
12 - Below property should be in zynqmp-firmware node.
13 - #power-domain-cells: Number of cells in a PM domain specifier. Must be 1.
16 include/dt-bindings/power/xlnx-zynqmp-power.h.
18 -------
20 -------
22 firmware {
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/freebsd/sys/contrib/device-tree/Bindings/gpio/
H A Dxlnx,zynqmp-gpio-modepin.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/xlnx,zynqmp
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/freebsd/sys/contrib/device-tree/Bindings/remoteproc/
H A Dxlnx,zynqmp-r5fss.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/xlnx,zynqmp-r5fss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ben Levinsky <ben.levinsky@amd.com>
11 - Tanmay Shah <tanmay.shah@amd.com>
14 The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for
15 real-time processing based on the Cortex-R5F processor core from ARM.
16 The Cortex-R5F processor implements the Arm v7-R architecture and includes a
17 floating-point unit that implements the Arm VFPv3 instruction set.
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/freebsd/sys/contrib/device-tree/src/arm64/xilinx/
H A Dzynqmp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP
5 * (C) Copyright 2014 - 2021, Xilinx, Inc.
15 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/interrupt-controller/irq.h>
19 #include <dt-bindings/power/xlnx-zynqmp-power.h>
20 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
23 compatible = "xlnx,zynqmp";
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/freebsd/sys/contrib/device-tree/Bindings/mailbox/
H A Dxlnx,zynqmp-ipi-mailbox.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/xlnx,zynqmp
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/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dxlnx,zynqmp-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/xlnx,zynqmp-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx ZynqMP Pinctrl
10 - Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
13 Please refer to pinctrl-bindings.txt in this directory for details of the
17 ZynqMP's pin configuration nodes act as a container for an arbitrary number of
21 parameters, such as pull-up, slew rate, etc.
31 const: xlnx,zynqmp-pinctrl
[all …]
/freebsd/sys/dev/clk/xilinx/
H A Dzynqmp_reset.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
45 #include <dev/firmware/xilinx/pm_defs.h>
186 rv = ZYNQMP_FIRMWARE_RESET_ASSERT(sc->parent, id, reset); in zynqmp_reset_assert()
199 rv = ZYNQMP_FIRMWARE_RESET_GET_STATUS(sc->parent, id, reset); in zynqmp_reset_is_asserted()
210 if (!ofw_bus_is_compatible(dev, "xlnx,zynqmp-reset")) in zynqmp_reset_probe()
212 device_set_desc(dev, "ZynqMP Reset Controller"); in zynqmp_reset_probe()
223 sc->dev = dev; in zynqmp_reset_attach()
224 sc->parent = device_get_parent(dev); in zynqmp_reset_attach()
H A Dzynqmp_clock.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
53 #include <dev/firmware/xilinx/pm_defs.h>
80 * Clock IDs in the firmware starts at 0 but
85 #define CLK_ID_TO_ZYNQMP(x) ((x) - 1)
114 device_t firmware; member
147 if (ZYNQMP_GET_NODE_TYPE(clkdef->topology[i]) == CLK_NODE_TYPE_NULL) in zynqmp_clk_register()
150 zynqclk->id = clkdef->clkdef.id; in zynqmp_clk_register()
153 zynqclk->parent_cnt = clkdef->clkdef.parent_cnt; in zynqmp_clk_register()
154 zynqclk->parent_names = clkdef->clkdef.parent_names; in zynqmp_clk_register()
[all …]
/freebsd/sys/dev/firmware/xilinx/
H A Dzynqmp_firmware.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
47 #include <dev/firmware/xilinx/pm_defs.h>
122 /* Firmware methods */
131 device_printf(sc->dev, "SMC Call fail %d\n", rv); in zynqmp_get_api_version()
134 device_printf(sc->dev, "API version = %d.%d\n", in zynqmp_get_api_version()
148 device_printf(sc->dev, "SMC Call fail %d\n", rv); in zynqmp_get_chipid()
151 device_printf(sc->dev, "ID Code = %x Version = %x\n", in zynqmp_get_chipid()
165 device_printf(sc->dev, "SMC Call fail %d\n", rv); in zynqmp_get_trustzone_version()
168 device_printf(sc->dev, "Trustzone Version = %x\n", in zynqmp_get_trustzone_version()
[all …]
H A Dpm_defs.h2 * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
4 * SPDX-License-Identifier: BSD-3-Clause
7 /* ZynqMP power management enums and defines */
28 /* Expected version of firmware APIs */
30 /* Expected version of firmware API for feature check */
101 /* API to query information from firmware */