Searched +full:zynqmp +full:- +full:ddrc +full:- +full:2 (Results 1 – 1 of 1) sorted by relevance
1 // SPDX-License-Identifier: GPL-2.0-only6 * Copyright (C) 2012 - 2014 Xilinx, Inc.56 #define CTRL_BW_SHIFT 292 #define DDR_ECC_INTR_SELF_CLEAR BIT(2)94 /* ZynqMP Enhanced DDR memory controller registers that are relevant to ECC */140 #define ECC_CTRL_CLR_CE_ERRCNT BIT(2)144 #define DDRCTL_EWDTH_16 2200 /* DDRC Software control register */203 /* DDRC ECC CE & UE poison mask */207 /* DDRC Device config masks */[all …]