Searched +full:zynqmp +full:- +full:ddrc +full:- +full:2 (Results 1 – 2 of 2) sorted by relevance
1 // SPDX-License-Identifier: GPL-2.0-only6 * Copyright (C) 2012 - 2014 Xilinx, Inc.56 #define CTRL_BW_SHIFT 292 #define DDR_ECC_INTR_SELF_CLEAR BIT(2)94 /* ZynqMP Enhanced DDR memory controller registers that are relevant to ECC */140 #define ECC_CTRL_CLR_CE_ERRCNT BIT(2)144 #define DDRCTL_EWDTH_16 2200 /* DDRC Software control register */203 /* DDRC ECC CE & UE poison mask */207 /* DDRC Device config masks */[all …]
5 ---------------------------------------------------21 W: *Web-page* with status/info23 B: URI for where to file *bugs*. A web-page with detailed bug28 patches to the given subsystem. This is either an in-tree file,29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst46 N: [^a-z]tegra all files whose path contains tegra64 ----------------83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)85 L: linux-scsi@vger.kernel.org88 F: drivers/scsi/3w-*[all …]