Searched +full:zynqmp +full:- +full:ddrc +full:- +full:2 (Results 1 – 2 of 2) sorted by relevance
1 # SPDX-License-Identifier: GPL-2.0-only3 ---4 $id: http://devicetree.org/schemas/memory-controllers/synopsys,ddrc-ecc.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Krzysztof Kozlowski <krzk@kernel.org>11 - Manish Narani <manish.narani@xilinx.com>12 - Michal Simek <michal.simek@xilinx.com>15 The ZynqMP DDR ECC controller has an optional ECC support in 64-bit and16 32-bit bus width configurations.18 The Zynq DDR ECC controller has an optional ECC support in half-bus width[all …]
1 // SPDX-License-Identifier: GPL-2.0+3 * dts file for Xilinx ZynqMP5 * (C) Copyright 2014 - 2021, Xilinx, Inc.11 * published by the Free Software Foundation; either version 2 of15 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>16 #include <dt-bindings/gpio/gpio.h>17 #include <dt-bindings/interrupt-controller/arm-gic.h>18 #include <dt-bindings/interrupt-controller/irq.h>19 #include <dt-bindings/power/xlnx-zynqmp-power.h>20 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>[all …]