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Searched +full:zynq +full:- +full:spi +full:- +full:r1p6 (Results 1 – 5 of 5) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/spi/
H A Dspi-cadence.txt1 Cadence SPI controller Device Tree Bindings
2 -------------------------------------------
5 - compatible : Should be "cdns,spi-r1p6" or "xlnx,zynq-spi-r1p6".
6 - reg : Physical base address and size of SPI registers map.
7 - interrupts : Property with a value describing the interrupt
9 - clock-names : List of input clock names - "ref_clk", "pclk"
11 - clocks : Clock phandles (see clock bindings for details).
14 - num-cs : Number of chip selects used.
17 - is-decoded-cs : Flag to indicate whether decoder is used or not.
21 spi@e0007000 {
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H A Dspi-cadence.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-cadence.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence SPI controller
10 - Michal Simek <michal.simek@amd.com>
13 - $ref: spi-controller.yaml#
18 - cdns,spi-r1p6
19 - xlnx,zynq-spi-r1p6
27 clock-names:
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/freebsd/sys/contrib/device-tree/src/arm/xilinx/
H A Dzynq-7000.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
7 #address-cells = <1>;
8 #size-cells = <1>;
9 compatible = "xlnx,zynq-7000";
12 #address-cells = <1>;
13 #size-cells = <0>;
16 compatible = "arm,cortex-a9";
20 clock-latency = <1000>;
21 cpu0-supply = <&regulator_vccpint>;
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/freebsd/sys/arm/xilinx/
H A Dzy7_spi.c1 /*-
47 #include <dev/spibus/spi.h>
54 {"xlnx,zynq-spi-1.0", 1},
55 {"cdns,spi-r1p6", 1},
85 #define SPI_SC_LOCK(sc) mtx_lock(&(sc)->sc_mtx)
86 #define SPI_SC_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx)
88 mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev), NULL, MTX_DEF)
89 #define SPI_SC_LOCK_DESTROY(sc) mtx_destroy(&(sc)->sc_mtx)
90 #define SPI_SC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED)
92 #define RD4(sc, off) (bus_read_4((sc)->mem_res, (off)))
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/freebsd/sys/contrib/device-tree/src/arm64/xilinx/
H A Dzynqmp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2014 - 2021, Xilinx, Inc.
15 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/interrupt-controller/irq.h>
19 #include <dt-bindings/power/xlnx-zynqmp-power.h>
20 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
24 #address-cells = <2>;
25 #size-cells = <2>;
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