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/freebsd/sys/contrib/device-tree/Bindings/spi/
H A Dxlnx,zynq-qspi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/xlnx,zynq-qspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Zynq QSPI controller
10 The Xilinx Zynq QSPI controller is used to access multi-bit serial flash
14 - $ref: spi-controller.yaml#
17 - Michal Simek <michal.simek@amd.com>
22 const: xlnx,zynq-qspi-1.0
25 maxItems: 1
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H A Dspi-zynq-qspi.txt1 Xilinx Zynq QSPI controller Device Tree Bindings
2 -------------------------------------------------------------------
5 - compatible : Should be "xlnx,zynq-qspi-1.0".
6 - reg : Physical base address and size of QSPI registers map.
7 - interrupts : Property with a value describing the interrupt
9 - clock-names : List of input clock names - "ref_clk", "pclk"
11 - clocks : Clock phandles (see clock bindings for details).
14 - num-cs : Number of chip selects used.
17 qspi: spi@e000d000 {
18 compatible = "xlnx,zynq-qspi-1.0";
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H A Dspi-zynqmp-qspi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-zynqmp-qspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Zynq UltraScale+ MPSoC GQSPI controller
10 - Michal Simek <michal.simek@amd.com>
13 - $ref: spi-controller.yaml#
18 - xlnx,versal-qspi-1.0
19 - xlnx,zynqmp-qspi-1.0
25 maxItems: 1
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H A Dspi-zynqmp-qspi.txt1 Xilinx Zynq UltraScale+ MPSoC GQSPI controller Device Tree Bindings
2 -------------------------------------------------------------------
5 - compatible : Should be "xlnx,zynqmp-qspi-1.0".
6 - reg : Physical base address and size of GQSPI registers map.
7 - interrupts : Property with a value describing the interrupt
9 - clock-names : List of input clock names - "ref_clk", "pclk"
11 - clocks : Clock phandles (see clock bindings for details).
14 - num-cs : Number of chip selects used.
17 qspi: spi@ff0f0000 {
18 compatible = "xlnx,zynqmp-qspi-1.0";
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/freebsd/sys/contrib/device-tree/Bindings/reset/
H A Dzynq-reset.txt1 Xilinx Zynq Reset Manager
3 The Zynq AP-SoC has several different resets.
5 See Chapter 26 of the Zynq TRM (UG585) for more information about Zynq resets.
8 - compatible: "xlnx,zynq-reset"
9 - reg: SLCR offset and size taken via syscon <0x200 0x48>
10 - syscon: <&slcr>
11 This should be a phandle to the Zynq's SLCR registers.
12 - #reset-cells: Must be 1
14 The Zynq Reset Manager needs to be a childnode of the SLCR.
18 compatible = "xlnx,zynq-reset";
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/freebsd/sys/contrib/device-tree/src/arm/xilinx/
H A Dzynq-7000.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
7 #address-cells = <1>;
8 #size-cells = <1>;
9 compatible = "xlnx,zynq-7000";
12 #address-cells = <1>;
13 #size-cells = <0>;
16 compatible = "arm,cortex-a9";
20 clock-latency = <1000>;
21 cpu0-supply = <&regulator_vccpint>;
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/freebsd/sys/dts/arm/
H A Dzynq-7000.dtsi1 /*-
8 * 1. Redistributions of source code must retain the above copyright
29 compatible = "xlnx,zynq-7000";
30 #address-cells = <1>;
31 #size-cells = <1>;
32 interrupt-parent = <&GIC>;
38 // Zynq PS System registers.
42 compatible = "simple-bus";
43 #address-cells = <1>;
44 #size-cells = <1>;
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/freebsd/sys/arm/xilinx/
H A Dzy7_qspi.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
10 * 1. Redistributions of source code must retain the above copyright
31 * This is a driver for the Quad-SPI Flash Controller in the Xilinx
32 * Zynq-7000 SoC.
63 {"xlnx,zy7_qspi", 1},
64 {"xlnx,zynq-qspi-1.0", 1},
98 #define QSPI_SC_LOCK(sc) mtx_lock(&(sc)->sc_mtx)
99 #define QSPI_SC_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx)
101 mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev), NULL, MTX_DEF)
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/freebsd/sys/contrib/device-tree/src/arm64/xilinx/
H A Dzynqmp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2014 - 2021, Xilinx, Inc.
15 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/interrupt-controller/irq.h>
19 #include <dt-bindings/power/xlnx-zynqmp-power.h>
20 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
24 #address-cells = <2>;
25 #size-cells = <2>;
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