Searched +full:zynq +full:- +full:ddrc +full:- +full:a05 (Results 1 – 4 of 4) sorted by relevance
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause3 ---4 $id: http://devicetree.org/schemas/memory-controller[all...]
3 The ZynqMP DDR ECC controller has an optional ECC support in 64-bit and 32-bit6 The Zynq DDR ECC controller has an optional ECC support in half-bus width7 (16-bit) configuration.13 - compatible: One of:14 - 'xlnx,zynq-ddrc-a05' : Zynq DDR ECC controller15 - 'xlnx,zynqmp-ddrc-2.40a' : ZynqMP DDR ECC controller16 - reg: Should contain DDR controller registers location and length.18 Required properties for "xlnx,zynqmp-ddrc-2.40a":19 - interrupts: Property with a value describing the interrupt number.22 memory-controller@f8006000 {[all …]
1 # SPDX-License-Identifier: GPL-2.0-only3 ---4 $id: http://devicetree.org/schemas/memory-controllers/synopsys,ddrc-ecc.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Krzysztof Kozlowski <krzk@kernel.org>11 - Manish Narani <manish.narani@xilinx.com>12 - Michal Simek <michal.simek@xilinx.com>15 The ZynqMP DDR ECC controller has an optional ECC support in 64-bit and16 32-bit bus width configurations.18 The Zynq DDR ECC controller has an optional ECC support in half-bus width[all …]
1 // SPDX-License-Identifier: GPL-2.03 * Copyright (C) 2011 - 2014 Xilinx7 #address-cells = <1>;8 #size-cells = <1>;9 compatible = "xlnx,zynq-7000";12 #address-cells = <1>;13 #size-cells = <0>;16 compatible = "arm,cortex-a9";20 clock-latency = <1000>;21 cpu0-supply = <®ulator_vccpint>;[all …]