Searched +full:xtal +full:- +full:load +full:- +full:pf (Results 1 – 3 of 3) sorted by relevance
| /freebsd/sys/contrib/device-tree/Bindings/clock/ |
| H A D | ti,cdce925.txt | 6 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt 15 - compatible: Shall be one of the following: 16 - "ti,cdce913": 1-PLL, 3 Outputs 17 - "ti,cdce925": 2-PLL, 5 Outputs 18 - "ti,cdce937": 3-PLL, 7 Outputs 19 - "ti,cdce949": 4-PLL, 9 Outputs 20 - reg: I2C device address. 21 - clocks: Points to a fixed parent clock that provides the input frequency. 22 - #clock-cells: From common clock bindings: Shall be 1. 25 - xtal-load-pf: Crystal load-capacitor value to fine-tune performance on a [all …]
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| H A D | ti,cdce925.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schema [all...] |
| /freebsd/sys/dev/qlnx/qlnxe/ |
| H A D | reg_addr.h | 2 * Copyright (c) 2017-2018 Cavium, Inc. 78 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl… 79 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea… 80 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn… 81 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea… 83 …Load, if a value of 0xFFFF is loaded to this field and a value of 0xFFFF is loaded to the [DEVID] … 88 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … 90 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 102 … (0x1<<2) // Bus master enable. If the PF or any of its VFs tr… 116 … (0x1<<9) // Fast back-to-back transaction ena… [all …]
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