Searched +full:xmem +full:- +full:read +full:- +full:wait +full:- +full:cycles (Results 1 – 2 of 2) sorted by relevance
1 // SPDX-License-Identifier: GPL-2.0-only41 * Bits 31-28: RECOVERY recovery cycles (0 = 1, 1 = 2 etc) this is the time the42 * memory continues to drive the data bus after OE is de-asserted.43 * Inserted when reading one CS and switching to another CS or read45 * Bits 27-24: WR_HOLD write hold cycles, these are extra cycles inserted after49 * Bits 23-16: WR_DELTA initial latency for write cycles inserted for the first51 * Bits 15-8: RD_DELTA initial latency for read cycles inserted for the first52 * read to a page or burst memory53 * Bits 7-4: WR_WAIT number of wait cycles for every write access, 0=1 cycle54 * so 1 thru 16 cycles.[all …]
1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2 #include <dt-bindings/input/input.h>3 #include <dt-bindings/gpio/gpio.h>4 #include <dt-bindings/leds/common.h>5 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>6 #include <dt-bindings/pinctrl/qcom,pmic-mpp.h>7 #include "qcom-msm8660.dtsi"12 compatible = "qcom,apq8060-dragonboard", "qcom,msm8660";19 stdout-path = "serial0:115200n8";23 vph: regulator-fixed {[all …]