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Searched +full:xlnx +full:- +full:zynqmp +full:- +full:resets (Results 1 – 13 of 13) sorted by relevance

/freebsd/sys/contrib/device-tree/src/arm64/xilinx/
H A Dzynqmp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP
5 * (C) Copyright 2014 - 2021, Xilinx, Inc.
15 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/interrupt-controller/irq.h>
19 #include <dt-bindings/power/xlnx-zynqmp-power.h>
20 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
23 compatible = "xlnx,zynqmp";
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/freebsd/sys/contrib/device-tree/Bindings/usb/
H A Ddwc3-xilinx.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/dwc3-xilinx.yaml#
5 $schema: http://devicetree.org/meta-schema
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H A Ddwc3-xilinx.txt4 - compatible: May contain "xlnx,zynqmp-dwc3" or "xlnx,versal-dwc3"
5 - reg: Base address and length of the register control block
6 - clocks: A list of phandles for the clocks listed in clock-names
7 - clock-names: Should contain the following:
12 - resets: A list of phandles for resets listed in reset-names
13 - reset-names:
23 - dma-coherent: Enable this flag if CCI is enabled in design. Adding this
25 Xilinx USB 3.0 IP - USB coherency register to enable CCI.
26 - interrupt-names: Should contain the following:
34 #address-cells = <0x2>;
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H A Ddwc3.txt3 DWC3- USB3 CONTROLLER. Complies to the generic USB binding properties
7 - compatible: must be "snps,dwc3"
8 - reg : Address and length of the register set for the device
9 - interrupts: Interrupts used by the dwc3 controller.
10 - clock-names: list of clock names. Ideally should be "ref",
12 - clocks: list of phandle and clock specifier pairs corresponding to
13 entries in the clock-names property.
16 clocks are optional if the parent node (i.e. glue-layer) is compatible to
18 "cavium,octeon-7130-usb-uctl"
20 "samsung,exynos5250-dwusb3"
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/freebsd/sys/contrib/device-tree/Bindings/reset/
H A Dxlnx,zynqmp-reset.txt1 --------------------------------------------------------------------------
3 --------------------------------------------------------------------------
4 The Zynq UltraScale+ MPSoC and Versal has several different resets.
7 about zynqmp resets.
13 - compatible: "xlnx,zynqmp-reset" for Zynq UltraScale+ MPSoC platform
14 "xlnx,versal-reset" for Versal platform
15 - #reset-cells: Specifies the number of cells needed to encode reset
18 -------
20 -------
23 zynqmp_firmware: zynqmp-firmware {
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H A Dxlnx,zynqmp-reset.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/reset/xlnx,zynqm
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/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dcdns,macb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Ferre <nicolas.ferre@microchip.com>
11 - Claudiu Beznea <claudiu.beznea@microchip.com>
16 - items:
17 - enum:
18 - cdns,at91rm9200-emac # Atmel at91rm9200 SoC
19 - const: cdns,emac # Generic
21 - items:
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/freebsd/sys/contrib/device-tree/Bindings/display/xlnx/
H A Dxlnx,zynqmp-dpsub.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/xlnx/xlnx,zynqmp-dpsub.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx ZynqMP DisplayPort Subsystem
10 The DisplayPort subsystem of Xilinx ZynqMP (Zynq UltraScale+ MPSoC)
14 +------------------------------------------------------------+
15 +--------+ | +----------------+ +-----------+ |
16 | DPDMA | --->| | --> | Video | Video +-------------+ |
17 | 4x vid | | | | | Rendering | -+--> | | | +------+
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/freebsd/sys/contrib/device-tree/Bindings/ata/
H A Dceva,ahci-1v84.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/ceva,ahci-
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/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Dsnps,dw-umctl2-ddrc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/snps,dw-umctl2-ddrc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare Universal Multi-Protocol Memory Controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Michal Simek <michal.simek@amd.com>
17 16-bits or 32-bits or 64-bits wide.
19 For instance the ZynqMP DDR controller is based on the DW uMCTL2 v2.40a
20 controller. It has an optional SEC/DEC ECC support in 64- and 32-bits
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/freebsd/sys/contrib/device-tree/Bindings/mmc/
H A Darasan,sdhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
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/freebsd/sys/contrib/device-tree/Bindings/serial/
H A Dcdns,uart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michal Simek <michal.simek@amd.com>
15 - description: UART controller for Zynq-7xxx SoC
17 - const: xlnx,xuartps
18 - const: cdns,uart-r1p8
19 - description: UART controller for Zynq Ultrascale+ MPSoC
21 - const: xlnx,zynqmp-uart
22 - const: cdns,uart-r1p12
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/freebsd/sys/contrib/device-tree/Bindings/gpu/
H A Darm,mali-utgard.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/gpu/arm,mali-utgard.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ro
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