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/linux/Documentation/devicetree/bindings/net/
H A Dairoha,en7581-eth.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/airoha,en7581-eth.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Bianconi <lorenzo@kernel.org>
14 These SoCs have multi-GMAC ports.
19 - airoha,en7581-eth
23 - description: Frame engine base address
24 - description: QDMA0 base address
25 - description: QDMA1 base address
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/linux/drivers/net/ethernet/myricom/myri10ge/
H A Dmyri10ge_mcp.h1 /* SPDX-License-Identifier: GPL-2.0 */
109 #define MXGEFW_ETH_SEND_OFFSET(n) (MXGEFW_ETH_SEND(n) - MXGEFW_ETH_SEND_4)
160 * (plus mtu & mac address) must have been exchanged prior
192 * command return data = repetitions (MSH), 0.5-ms ticks (LSH)
205 * or is equal to FF-FF-FF-FF-FF-FF
234 * the NIC to be able to receive maximum-sized packets.
239 /* data0 = number of slices n (0, 1, ..., n-1) to enable
242 * 1=use one MSI-X per queue.
287 * always has enough header buffer to store maximum-sized headers.
305 * obtained data is cached inside the xaui-xfi chip :
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H A Dmyri10ge.c2 * myri10ge.c: Myricom Myri-10G Ethernet driver.
4 * Copyright (C) 2005 - 2011 Myricom, Inc.
34 * http://www.myri.com/scs/download-Myri10GE.html
49 #include <linux/dma-mapping.h>
78 #define MYRI10GE_VERSION_STR "1.5.3-1.534"
135 int mask; /* number of rx slots -1 */
146 int mask; /* number of transmit slots -1 */
243 u8 mac_addr[ETH_ALEN]; /* eeprom mac address */
274 {[0 ... (MYRI10GE_MAX_BOARDS - 1)] = NULL };
281 MODULE_PARM_DESC(myri10ge_ecrc_enable, "Enable Extended CRC on PCI-E");
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/linux/Documentation/networking/
H A Dphy.rst9 to a MAC layer, which communicates with the physical connection through a
26 #. Increase code-reuse
27 #. Increase overall code-maintainability
67 for one of the users. (e.g. "git grep fsl,.*-mdio arch/powerpc/boot/dts/")
72 The Reduced Gigabit Medium Independent Interface (RGMII) is a 12-pin
78 the PHY driver and optionally the MAC driver, implement the required delay. The
83 internal delay by itself, it assumes that either the Ethernet MAC (if capable)
84 or the PCB traces insert the correct 1.5-2ns delay
97 * PHY devices may offer sub-nanosecond granularity in how they allow a
110 Ethernet MAC driver is capable of doing so, the correct phy_interface_t value
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/linux/drivers/net/ethernet/qlogic/netxen/
H A Dnetxen_nic.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (C) 2003 - 2009 NetXen, Inc.
4 * Copyright (C) 2009 - QLogic Corporation.
47 * 7:0 - major
48 * 15:8 - minor
49 * 31:16 - build (little endian)
60 (sizeof(struct rcv_desc) * (rds_ring)->num_desc)
62 (sizeof(struct netxen_rx_buffer) * rds_ring->num_desc)
64 (sizeof(struct status_desc) * (sds_ring)->num_desc)
66 (sizeof(struct netxen_cmd_buffer) * tx_ring->num_desc)
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/linux/drivers/net/ethernet/mediatek/
H A Dairoha_eth.c1 // SPDX-License-Identifier: GPL-2.0-only
490 (((_n) < 8) ? 0x0100 + ((_n) << 5) : 0x0b00 + (((_n) - 8) << 5))
493 (((_n) < 8) ? 0x0104 + ((_n) << 5) : 0x0b04 + (((_n) - 8) << 5))
502 (((_n) < 8) ? 0x0108 + ((_n) << 5) : 0x0b08 + (((_n) - 8) << 5))
507 (((_n) < 8) ? 0x010c + ((_n) << 5) : 0x0b0c + (((_n) - 8) << 5))
515 (((_n) < 16) ? 0x0200 + ((_n) << 5) : 0x0e00 + (((_n) - 16) << 5))
518 (((_n) < 16) ? 0x0204 + ((_n) << 5) : 0x0e04 + (((_n) - 16) << 5))
524 (((_n) < 16) ? 0x0208 + ((_n) << 5) : 0x0e08 + (((_n) - 16) << 5))
529 (((_n) < 16) ? 0x020c + ((_n) << 5) : 0x0e0c + (((_n) - 16) << 5))
532 (((_n) < 16) ? 0x0210 + ((_n) << 5) : 0x0e10 + (((_n) - 16) << 5))
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/linux/drivers/net/ethernet/sfc/siena/
H A Dmcdi_pcol.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2009-2018 Solarflare Communications Inc.
5 * Copyright 2019-2020 Xilinx Inc.
13 /* Power-on reset state */
35 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
38 /* The rest of these are firmware-defined */
46 /* Values to be written to the per-port status dword in shared
71 * | | \--- Response
72 * | \------- Error
73 * \------------------------------ Resync (always set)
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/linux/drivers/net/ethernet/sfc/
H A Dmcdi_pcol.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2009-2018 Solarflare Communications Inc.
5 * Copyright 2019-2020 Xilinx Inc.
13 /* Power-on reset state */
35 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
38 /* The rest of these are firmware-defined */
46 /* Values to be written to the per-port status dword in shared
71 * | | \--- Response
72 * | \------- Error
73 * \------------------------------ Resync (always set)
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