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/linux/drivers/media/usb/dvb-usb/
H A Daf9005-script.h19 {0xa180, 0x0, 0x8, 0xa},
20 {0xa181, 0x0, 0x8, 0xd7},
21 {0xa182, 0x0, 0x8, 0xa3},
22 {0xa0a0, 0x0, 0x8, 0x0},
27 {0xa20f, 0x0, 0x8, 0x40},
28 {0xa210, 0x0, 0x8, 0x8},
30 {0xa32c, 0x0, 0x8, 0x20},
31 {0xa32b, 0x0, 0x8, 0x15},
48 {0xa015, 0x0, 0x8, 0x50},
50 {0xa02a, 0x0, 0x8, 0x50},
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A Dgmc_7_1_sh_mask.h33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
44 #define MC_CONFIG__MC_RD_ENABLE__SHIFT 0x8
53 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP3_MASK 0x8
64 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP0__SHIFT 0x8
94 #define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_RD__SHIFT 0x8
123 #define MC_ARB_GECC2_STATUS__RSVD0_MASK 0x8
134 #define MC_ARB_GECC2_STATUS__CORR_CLEAR0__SHIFT 0x8
182 #define MC_ARB_GECC2_MISC__RMW_STALL_RELEASE__SHIFT 0x8
204 #define MC_ARB_GECC2_DEBUG2__ERR0_START__SHIFT 0x8
212 #define MC_ARB_PERF_CID__CH1__SHIFT 0x8
[all …]
H A Dgmc_8_1_sh_mask.h33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
44 #define MC_CONFIG__MC_RD_ENABLE__SHIFT 0x8
49 #define MC_ARB_ATOMIC__TC_GRP_EN_MASK 0x8
56 #define MC_ARB_ATOMIC__OUTSTANDING__SHIFT 0x8
65 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP3_MASK 0x8
76 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP0__SHIFT 0x8
106 #define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_RD__SHIFT 0x8
141 #define MC_ARB_GECC2_STATUS__RSVD0_MASK 0x8
152 #define MC_ARB_GECC2_STATUS__CORR_CLEAR0__SHIFT 0x8
200 #define MC_ARB_GECC2_MISC__RMW_STALL_RELEASE__SHIFT 0x8
[all …]
H A Dgmc_7_0_sh_mask.h33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
45 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP3_MASK 0x8
56 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP0__SHIFT 0x8
95 #define MC_ARB_GECC2_STATUS__RSVD0_MASK 0x8
106 #define MC_ARB_GECC2_STATUS__CORR_CLEAR0__SHIFT 0x8
164 #define MC_ARB_GECC2_DEBUG2__ERR0_START__SHIFT 0x8
192 #define MC_ARB_GECC2_CLI__NO_GECC_CLI1__SHIFT 0x8
202 #define MC_ARB_ADDR_SWIZ0__A10__SHIFT 0x8
218 #define MC_ARB_ADDR_SWIZ1__A18__SHIFT 0x8
258 #define MC_ARB_RTT_CNTL0__BREAK_ON_HARSH__SHIFT 0x8
[all …]
H A Dgmc_8_2_sh_mask.h33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
44 #define MC_CONFIG__MC_RD_ENABLE__SHIFT 0x8
49 #define MC_ARB_ATOMIC__TC_GRP_EN_MASK 0x8
56 #define MC_ARB_ATOMIC__OUTSTANDING__SHIFT 0x8
65 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP3_MASK 0x8
76 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP0__SHIFT 0x8
106 #define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_RD__SHIFT 0x8
141 #define MC_ARB_GECC2_STATUS__RSVD0_MASK 0x8
152 #define MC_ARB_GECC2_STATUS__CORR_CLEAR0__SHIFT 0x8
200 #define MC_ARB_GECC2_MISC__RMW_STALL_RELEASE__SHIFT 0x8
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_4_1_sh_mask.h43 #define BUS_CNTL__PMI_MEM_DIS_MASK 0x8
54 #define BUS_CNTL__BIF_ERR_RTR_BKPRESSURE_EN__SHIFT 0x8
93 #define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK 0x8
101 #define HW_DEBUG__HW_03_DEBUG_MASK 0x8
112 #define HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
181 #define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK 0x8
186 #define INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT 0x8
199 #define BIF_DEBUG_CNTL__DEBUG_PAD_SEL_MASK 0x8
210 #define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK1__SHIFT 0x8
220 #define BIF_DEBUG_MUX__DEBUG_MUX_BLK2__SHIFT 0x8
[all …]
H A Dbif_5_0_sh_mask.h47 #define BUS_CNTL__PMI_MEM_DIS_MASK 0x8
58 #define BUS_CNTL__BIF_ERR_RTR_BKPRESSURE_EN__SHIFT 0x8
98 #define BIF_RLC_INTR_CNTL__RLC_VM_IDLE_INTERRUPT__SHIFT 0x8
118 #define BX_RESET_EN__FLR_TWICE_EN__SHIFT 0x8
129 #define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK 0x8
137 #define HW_DEBUG__HW_03_DEBUG_MASK 0x8
148 #define HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
217 #define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK 0x8
222 #define INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT 0x8
237 #define BIF_DEBUG_CNTL__DEBUG_PAD_SEL_MASK 0x8
[all …]
H A Dbif_5_1_sh_mask.h43 #define BUS_CNTL__PMI_MEM_DIS_MASK 0x8
54 #define BUS_CNTL__BIF_ERR_RTR_BKPRESSURE_EN__SHIFT 0x8
93 #define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK 0x8
101 #define HW_DEBUG__HW_03_DEBUG_MASK 0x8
112 #define HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
181 #define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK 0x8
186 #define INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT 0x8
201 #define BIF_DEBUG_CNTL__DEBUG_PAD_SEL_MASK 0x8
212 #define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK1__SHIFT 0x8
222 #define BIF_DEBUG_MUX__DEBUG_MUX_BLK2__SHIFT 0x8
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/smu/
H A Dsmu_7_0_0_sh_mask.h34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
46 #define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN__SHIFT 0x8
58 #define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN__SHIFT 0x8
70 #define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN__SHIFT 0x8
81 #define GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK 0x8
92 #define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK__SHIFT 0x8
107 #define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK 0x8
186 #define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN__SHIFT 0x8
196 #define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT__SHIFT 0x8
213 #define SPLL_CNTL_MODE__SPLL_FASTEN_MASK 0x8
[all …]
H A Dsmu_7_1_3_sh_mask.h44 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
56 #define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN__SHIFT 0x8
68 #define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN__SHIFT 0x8
80 #define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN__SHIFT 0x8
88 #define CG_MCLK_CNTL__MCLK_DIR_CNTL_EN__SHIFT 0x8
103 #define GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK 0x8
114 #define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK__SHIFT 0x8
131 #define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK 0x8
206 #define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN__SHIFT 0x8
212 #define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT__SHIFT 0x8
[all …]
H A Dsmu_7_1_2_sh_mask.h34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
46 #define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN__SHIFT 0x8
58 #define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN__SHIFT 0x8
70 #define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN__SHIFT 0x8
81 #define GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK 0x8
92 #define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK__SHIFT 0x8
107 #define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK 0x8
180 #define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN__SHIFT 0x8
186 #define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT__SHIFT 0x8
205 #define SPLL_CNTL_MODE__SPLL_FASTEN_MASK 0x8
[all …]
H A Dsmu_7_0_1_sh_mask.h34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
46 #define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN__SHIFT 0x8
58 #define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN__SHIFT 0x8
70 #define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN__SHIFT 0x8
81 #define GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK 0x8
92 #define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK__SHIFT 0x8
107 #define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK 0x8
180 #define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN__SHIFT 0x8
186 #define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT__SHIFT 0x8
205 #define SPLL_CNTL_MODE__SPLL_FASTEN_MASK 0x8
[all …]
H A Dsmu_7_1_0_sh_mask.h34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
46 #define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN__SHIFT 0x8
58 #define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN__SHIFT 0x8
70 #define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN__SHIFT 0x8
81 #define GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK 0x8
92 #define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK__SHIFT 0x8
107 #define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK 0x8
180 #define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN__SHIFT 0x8
186 #define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT__SHIFT 0x8
203 #define SPLL_CNTL_MODE__SPLL_FASTEN_MASK 0x8
[all …]
H A Dsmu_7_1_1_sh_mask.h34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
46 #define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN__SHIFT 0x8
58 #define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN__SHIFT 0x8
70 #define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN__SHIFT 0x8
81 #define GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK 0x8
92 #define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK__SHIFT 0x8
107 #define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK 0x8
180 #define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN__SHIFT 0x8
186 #define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT__SHIFT 0x8
203 #define SPLL_CNTL_MODE__SPLL_FASTEN_MASK 0x8
[all …]
/linux/include/linux/mlx5/
H A Dmlx5_ifc_fpga.h37 u8 reserved_at_10[0x8];
38 u8 total_rcv_credits[0x8];
61 u8 fpga_id[0x8];
87 u8 reserved_at_380[0x8];
121 u8 reserved_at_0[0x8];
122 u8 operation[0x8];
123 u8 reserved_at_10[0x8];
124 u8 status[0x8];
126 u8 reserved_at_20[0x8];
127 u8 flash_select_admin[0x8];
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_8_0_sh_mask.h128 #define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_WRITE_EN__SHIFT 0x8
149 #define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK 0x8
158 #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8
166 #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT 0x8
178 #define DC_ABM1_CNTL__ABM1_SOURCE_SELECT__SHIFT 0x8
184 #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT 0x8
240 #define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT 0x8
244 #define DC_ABM1_DEBUG_MISC__ABM1_LS_FORCE_INTERRUPT__SHIFT 0x8
254 #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT 0x8
268 #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT 0x8
[all …]
H A Ddce_11_0_sh_mask.h89 #define DCPG_INTERRUPT_STATUS__DCFE1_POWER_DOWN_INT_OCCURRED_MASK 0x8
100 #define DCPG_INTERRUPT_STATUS__DCFE4_POWER_UP_INT_OCCURRED__SHIFT 0x8
121 #define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_DOWN_INT_CLEAR_MASK 0x8
132 #define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_UP_INT_MASK__SHIFT 0x8
196 #define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_WRITE_EN__SHIFT 0x8
217 #define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK 0x8
226 #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8
234 #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT 0x8
246 #define DC_ABM1_CNTL__ABM1_SOURCE_SELECT__SHIFT 0x8
252 #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT 0x8
[all …]
H A Ddce_10_0_sh_mask.h128 #define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_WRITE_EN__SHIFT 0x8
149 #define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK 0x8
158 #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8
166 #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT 0x8
178 #define DC_ABM1_CNTL__ABM1_SOURCE_SELECT__SHIFT 0x8
184 #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT 0x8
240 #define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT 0x8
244 #define DC_ABM1_DEBUG_MISC__ABM1_LS_FORCE_INTERRUPT__SHIFT 0x8
254 #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT 0x8
268 #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT 0x8
[all …]
H A Ddce_11_2_sh_mask.h117 #define DCPG_INTERRUPT_STATUS__DCFE1_POWER_DOWN_INT_OCCURRED_MASK 0x8
128 #define DCPG_INTERRUPT_STATUS__DCFE4_POWER_UP_INT_OCCURRED__SHIFT 0x8
153 #define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_DOWN_INT_CLEAR_MASK 0x8
164 #define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_UP_INT_MASK__SHIFT 0x8
236 #define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_WRITE_EN__SHIFT 0x8
257 #define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK 0x8
266 #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8
274 #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT 0x8
286 #define DC_ABM1_CNTL__ABM1_SOURCE_SELECT__SHIFT 0x8
292 #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT 0x8
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dpcs/
H A Ddpcs_4_2_3_sh_mask.h77 …0_DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN__SHIFT 0x8
91 …0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_PU_EN__SHIFT 0x8
109 …0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK__SHIFT 0x8
127 …0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_A__SHIFT 0x8
140 …0_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN__SHIFT 0x8
166 …0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_STATE__SHIFT 0x8
175 …0_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY2__SHIFT 0x8
184 …0_PANEL_PWRSEQ_DELAY2__PANEL_PWRUP_DELAY3__SHIFT 0x8
225 …0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT 0x8
236 …0_PANEL_PWRSEQ_REF_DIV2__MICROSECOND_TIME_BASE_DIV__SHIFT 0x8
[all …]
/linux/arch/powerpc/boot/dts/
H A Dmpc8308_p1m.dts50 interrupts = <77 0x8>;
92 interrupts = <18 0x8>;
98 reg = <0x2 0x0 0x8>;
99 interrupts = <48 0x8>;
118 interrupts = <14 0x8>;
132 interrupts = <15 0x8>;
159 interrupts = <38 0x8>;
175 interrupts = <32 0x8 33 0x8 34 0x8>;
186 interrupts = <17 0x8>;
191 interrupts = <19 0x8>;
[all …]
H A Dmpc8315erdb.dts53 interrupts = <77 0x8>;
115 interrupts = <14 0x8>;
136 interrupts = <16 0x8>;
186 interrupts = <38 0x8>;
200 interrupts = <32 0x8 33 0x8 34 0x8>;
214 interrupts = <20 0x8>;
220 interrupts = <19 0x8>;
241 interrupts = <35 0x8 36 0x8 37 0x8>;
266 interrupts = <9 0x8>;
276 interrupts = <10 0x8>;
[all …]
H A Dmpc5121.dtsi49 interrupts = <66 0x8>;
124 interrupts = <79 0x8 80 0x8>;
146 interrupts = <83 0x8>;
152 interrupts = <78 0x8>;
158 interrupts = <12 0x8>;
170 interrupts = <13 0x8>;
182 interrupts = <8 0x8>;
195 interrupts = <9 0x8>;
205 interrupts = <10 0x8>;
215 interrupts = <11 0x8>;
[all …]
H A Dmpc8308rdb.dts51 interrupts = <77 0x8>;
119 interrupts = <14 0x8>;
134 interrupts = <38 0x8>;
150 interrupts = <32 0x8 33 0x8 34 0x8>;
163 interrupts = <17 0x8>;
183 interrupts = <35 0x8 36 0x8 37 0x8>;
209 interrupts = <9 0x8>;
219 interrupts = <10 0x8>;
228 interrupts = <74 0x8>;
252 interrupts = < 0x43 0x8
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/nbio/
H A Dnbio_7_2_0_sh_mask.h41 …G_DEV0_RC_COMMAND__SERR_EN__SHIFT 0x8
61 …G_DEV0_RC_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
120 …G_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
130 …G_DEV0_RC_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
139 …G_DEV0_RC_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
205 …G_DEV0_RC_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT 0x8
226 …G_DEV0_RC_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
249 …G_DEV0_RC_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
267 …G_DEV0_RC_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
273 …G_DEV0_RC_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
[all …]

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