Home
last modified time | relevance | path

Searched full:x4 (Results 1 – 25 of 2677) sorted by relevance

12345678910>>...108

/linux/arch/x86/crypto/
H A Dserpent-sse2-x86_64-asm_64.S41 #define S0_1(x0, x1, x2, x3, x4) \ argument
42 movdqa x3, x4; \
44 pxor x4, x0; \
45 pxor x2, x4; \
46 pxor RNOT, x4; \
49 pxor x4, x1; \
51 #define S0_2(x0, x1, x2, x3, x4) \ argument
53 por x0, x4; \
58 pxor x4, x2; \
61 #define S1_1(x0, x1, x2, x3, x4) \ argument
[all …]
H A Dserpent-sse2-i586-asm_32.S42 #define K(x0, x1, x2, x3, x4, i) \ argument
43 get_key(i, 0, x4); \
46 pxor x4, x0; \
49 get_key(i, 3, x4); \
50 pxor x4, x3;
52 #define LK(x0, x1, x2, x3, x4, i) \ argument
53 movdqa x0, x4; \
55 psrld $(32 - 13), x4; \
56 por x4, x0; \
58 movdqa x2, x4; \
[all …]
H A Dserpent-avx2-asm_64.S51 #define S0_1(x0, x1, x2, x3, x4) \ argument
54 vpxor x2, x3, x4; \
55 vpxor RNOT, x4, x4; \
58 vpxor x4, x1, x1; \
60 #define S0_2(x0, x1, x2, x3, x4) \ argument
62 vpor x0, x4, x4; \
67 vpxor x4, x2, x2; \
70 #define S1_1(x0, x1, x2, x3, x4) \ argument
74 vpand tp, x1, x4; \
79 #define S1_2(x0, x1, x2, x3, x4) \ argument
[all …]
/linux/drivers/clk/rockchip/
H A Dclk.h30 #define BOOST_PLL_H_CON(x) ((x) * 0x4)
40 #define BOOST_PLL_L_CON(x) ((x) * 0x4 + 0x2c)
49 #define PX30_PLL_CON(x) ((x) * 0x4)
50 #define PX30_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
51 #define PX30_CLKGATE_CON(x) ((x) * 0x4 + 0x200)
54 #define PX30_SOFTRST_CON(x) ((x) * 0x4 + 0x300)
64 #define PX30_PMU_PLL_CON(x) ((x) * 0x4)
65 #define PX30_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x40)
66 #define PX30_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x80)
80 #define RV1103B_PMUCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1103B_PMUCRU_BASE)
[all …]
/linux/drivers/gpu/drm/kmb/
H A Dkmb_regs.h12 #define LCD_CONTROL (0x4 * 0x000)
52 #define LCD_INT_STATUS (0x4 * 0x001)
81 #define LCD_INT_ENABLE (0x4 * 0x002)
82 #define LCD_INT_CLEAR (0x4 * 0x003)
83 #define LCD_LINE_COUNT (0x4 * 0x004)
84 #define LCD_LINE_COMPARE (0x4 * 0x005)
85 #define LCD_VSTATUS (0x4 * 0x006)
91 #define LCD_VSTATUS_COMPARE (0x4 * 0x007)
98 #define LCD_SCREEN_WIDTH (0x4 * 0x008)
99 #define LCD_SCREEN_HEIGHT (0x4 * 0x009)
[all …]
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dapm,xgene1-msi.yaml38 interrupts = <0x0 0x10 0x4>,
39 <0x0 0x11 0x4>,
40 <0x0 0x12 0x4>,
41 <0x0 0x13 0x4>,
42 <0x0 0x14 0x4>,
43 <0x0 0x15 0x4>,
44 <0x0 0x16 0x4>,
45 <0x0 0x17 0x4>,
46 <0x0 0x18 0x4>,
47 <0x0 0x19 0x4>,
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6sl-pinfunc.h17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
25 #define MX6SL_PAD_AUD_RXC__I2C3_SDA 0x050 0x2a8 0x730 0x4 0x0
33 #define MX6SL_PAD_AUD_RXD__SD1_LCTL 0x054 0x2ac 0x000 0x4 0x0
40 #define MX6SL_PAD_AUD_RXFS__I2C3_SCL 0x058 0x2b0 0x72c 0x4 0x0
48 #define MX6SL_PAD_AUD_TXC__SD2_LCTL 0x05c 0x2b4 0x000 0x4 0x0
55 #define MX6SL_PAD_AUD_TXD__SD4_LCTL 0x060 0x2b8 0x000 0x4 0x0
62 #define MX6SL_PAD_AUD_TXFS__SD3_LCTL 0x064 0x2bc 0x000 0x4 0x0
69 #define MX6SL_PAD_ECSPI1_MISO__SD2_WP 0x068 0x358 0x834 0x4 0x0
76 #define MX6SL_PAD_ECSPI1_MOSI__SD2_VSELECT 0x06c 0x35c 0x000 0x4 0x0
83 #define MX6SL_PAD_ECSPI1_SCLK__SD2_RESET 0x070 0x360 0x000 0x4 0x0
[all …]
H A Dimxrt1050-pinfunc.h21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0
28 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXIO1_D01 0x018 0x208 0x000 0x4 0x0
35 #define MXRT1050_IOMUXC_GPIO_EMC_02_FLEXIO1_D02 0x01C 0x20C 0x000 0x4 0x0
42 #define MXRT1050_IOMUXC_GPIO_EMC_03_FLEXIO1_D03 0x020 0x210 0x000 0x4 0x0
49 #define MXRT1050_IOMUXC_GPIO_EMC_04_FLEXIO1_D04 0x024 0x214 0x000 0x4 0x0
56 #define MXRT1050_IOMUXC_GPIO_EMC_05_FLEXIO1_D05 0x028 0x218 0x000 0x4 0x0
63 #define MXRT1050_IOMUXC_GPIO_EMC_06_FLEXIO1_D06 0x02C 0x21C 0x000 0x4 0x0
70 #define MXRT1050_IOMUXC_GPIO_EMC_07_FLEXIO1_D07 0x030 0x220 0x000 0x4 0x0
77 #define MXRT1050_IOMUXC_GPIO_EMC_08_FLEXIO1_D08 0x034 0x224 0x000 0x4 0x0
84 #define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXIO1_D09 0x038 0x228 0x000 0x4 0x0
[all …]
H A Dimx7d-pinfunc.h18 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0
23 #define MX7D_PAD_LPSR_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0
43 #define MX7D_PAD_LPSR_GPIO1_IO04__UART5_DTE_RTS 0x0010 0x0040 0x0710 0x3 0x4
44 #define MX7D_PAD_LPSR_GPIO1_IO04__I2C1_SCL 0x0010 0x0040 0x05D4 0x4 0x2
51 #define MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA 0x0014 0x0044 0x05D8 0x4 0x2
56 #define MX7D_PAD_LPSR_GPIO1_IO06__UART5_DCE_RX 0x0018 0x0048 0x0714 0x3 0x4
58 #define MX7D_PAD_LPSR_GPIO1_IO06__I2C2_SCL 0x0018 0x0048 0x05DC 0x4 0x2
66 #define MX7D_PAD_LPSR_GPIO1_IO07__I2C2_SDA 0x001C 0x004C 0x05E0 0x4 0x2
74 #define MX7D_PAD_GPIO1_IO08__I2C3_SCL 0x0014 0x026C 0x05E4 0x4 0x0
82 #define MX7D_PAD_GPIO1_IO09__I2C3_SDA 0x0018 0x0270 0x05E8 0x4 0x0
[all …]
H A Dimx6sll-pinfunc.h23 #define MX6SLL_PAD_REF_CLK_24M__CCM_PMIC_READY 0x0018 0x02E0 0x05AC 0x4 0x0
30 #define MX6SLL_PAD_REF_CLK_32K__SD1_LCTL 0x001C 0x02E4 0x0000 0x4 0x0
36 #define MX6SLL_PAD_PWM1__CSI_MCLK 0x0020 0x02E8 0x0000 0x4 0x0
42 #define MX6SLL_PAD_KEY_COL0__SD1_CD_B 0x0024 0x02EC 0x0770 0x4 0x1
47 #define MX6SLL_PAD_KEY_ROW0__SD1_WP 0x0028 0x02F0 0x0774 0x4 0x1
52 #define MX6SLL_PAD_KEY_COL1__SD3_DATA4 0x002C 0x02F4 0x0784 0x4 0x0
58 #define MX6SLL_PAD_KEY_ROW1__SD3_DATA5 0x0030 0x02F8 0x0788 0x4 0x0
64 #define MX6SLL_PAD_KEY_COL2__SD3_DATA6 0x0034 0x02FC 0x078C 0x4 0x0
70 #define MX6SLL_PAD_KEY_ROW2__SD3_DATA7 0x0038 0x0300 0x0790 0x4 0x0
193 #define MX6SLL_PAD_EPDC_DATA12__UART2_DCE_RX 0x0094 0x035C 0x074C 0x1 0x4
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx93-pinfunc.h16 #define MX93_PAD_DAP_TDI__FLEXIO2_FLEXIO30 0x0000 0x01B0 0x0000 0x4 0x0
20 #define MX93_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31 0x0004 0x01B4 0x0000 0x4 0x0
24 #define MX93_PAD_DAP_TCLK_SWCLK__FLEXIO1_FLEXIO30 0x0008 0x01B8 0x0000 0x4 0x0
30 #define MX93_PAD_DAP_TDO_TRACESWO__FLEXIO1_FLEXIO31 0x000C 0x01BC 0x0000 0x4 0x0
37 #define MX93_PAD_GPIO_IO00__LPSPI6_PCS0 0x0010 0x01C0 0x0000 0x4 0x0
45 #define MX93_PAD_GPIO_IO01__LPSPI6_SIN 0x0014 0x01C4 0x0000 0x4 0x0
53 #define MX93_PAD_GPIO_IO02__LPSPI6_SOUT 0x0018 0x01C8 0x0000 0x4 0x0
61 #define MX93_PAD_GPIO_IO03__LPSPI6_SCK 0x001C 0x01CC 0x0000 0x4 0x0
69 #define MX93_PAD_GPIO_IO04__LPSPI7_PCS0 0x0020 0x01D0 0x0000 0x4 0x0
77 #define MX93_PAD_GPIO_IO05__LPSPI7_SIN 0x0024 0x01D4 0x0000 0x4 0x0
[all …]
H A Dimx8mn-pinfunc.h57 …ne MX8MN_IOMUXC_GPIO1_IO09_USDHC3_RESET_B 0x04C 0x2B4 0x000 0x4 0x0
65 …ne MX8MN_IOMUXC_GPIO1_IO11_USDHC3_VSELECT 0x054 0x2BC 0x000 0x4 0x0
77 …ne MX8MN_IOMUXC_GPIO1_IO14_USDHC3_CD_B 0x060 0x2C8 0x598 0x4 0x2
81 …ne MX8MN_IOMUXC_GPIO1_IO15_USDHC3_WP 0x064 0x2CC 0x5B8 0x4 0x2
87 …ne MX8MN_IOMUXC_ENET_MDC_SPDIF1_OUT 0x068 0x2D0 0x000 0x4 0x0
93 …ne MX8MN_IOMUXC_ENET_MDIO_SPDIF1_IN 0x06C 0x2D4 0x5CC 0x4 0x1
99 …ne MX8MN_IOMUXC_ENET_TD3_SPDIF1_EXT_CLK 0x070 0x2D8 0x568 0x4 0x1
161 …ne MX8MN_IOMUXC_SD1_CLK_UART1_DCE_TX 0x0A0 0x308 0x000 0x4 0x0
162 …ne MX8MN_IOMUXC_SD1_CLK_UART1_DTE_RX 0x0A0 0x308 0x4F4 0x4 0x4
166 …ne MX8MN_IOMUXC_SD1_CMD_UART1_DCE_RX 0x0A4 0x30C 0x4F4 0x4 0x5
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_4_1_sh_mask.h41 #define BUS_CNTL__PMI_IO_DIS_MASK 0x4
46 #define BUS_CNTL__PMI_BM_DIS__SHIFT 0x4
69 #define CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK 0x4
89 #define BX_RESET_EN__STY_RESET_EN_MASK 0x4
99 #define HW_DEBUG__HW_02_DEBUG_MASK 0x4
104 #define HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
184 #define INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT 0x4
197 #define BIF_DEBUG_CNTL__DEBUG_OUT_EN_MASK 0x4
202 #define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK1__SHIFT 0x4
231 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK 0x4
[all …]
/linux/drivers/pinctrl/mvebu/
H A Dpinctrl-armada-xp.c46 MPP_VAR_FUNCTION(0x4, "lcd", "d0", V_MV78230_PLUS)),
50 MPP_VAR_FUNCTION(0x4, "lcd", "d1", V_MV78230_PLUS)),
54 MPP_VAR_FUNCTION(0x4, "lcd", "d2", V_MV78230_PLUS)),
58 MPP_VAR_FUNCTION(0x4, "lcd", "d3", V_MV78230_PLUS)),
62 MPP_VAR_FUNCTION(0x4, "lcd", "d4", V_MV78230_PLUS)),
66 MPP_VAR_FUNCTION(0x4, "lcd", "d5", V_MV78230_PLUS)),
70 MPP_VAR_FUNCTION(0x4, "lcd", "d6", V_MV78230_PLUS)),
74 MPP_VAR_FUNCTION(0x4, "lcd", "d7", V_MV78230_PLUS)),
78 MPP_VAR_FUNCTION(0x4, "lcd", "d8", V_MV78230_PLUS)),
82 MPP_VAR_FUNCTION(0x4, "lcd", "d9", V_MV78230_PLUS)),
[all …]
/linux/sound/soc/codecs/
H A Dtscs454.h19 #define R_IRQSTAT VIRT_ADDR(0x0, 0x4)
71 #define R_HSDDELAY VIRT_ADDR(0x1, 0x4)
103 #define R_DCCTL VIRT_ADDR(0x2, 0x4)
129 #define R_SPKCRWDH VIRT_ADDR(0x3, 0x4)
179 #define R_DACEQFILT VIRT_ADDR(0x4, 0x1)
180 #define R_DACCRWDL VIRT_ADDR(0x4, 0x2)
181 #define R_DACCRWDM VIRT_ADDR(0x4, 0x3)
182 #define R_DACCRWDH VIRT_ADDR(0x4, 0x4)
183 #define R_DACCRRDL VIRT_ADDR(0x4, 0x5)
184 #define R_DACCRRDM VIRT_ADDR(0x4, 0x6)
[all …]
/linux/arch/parisc/kernel/
H A Dhardware.c29 {HPHW_NPROC,0x01,0x4,0x0,"Indigo (840, 930)"},
30 {HPHW_NPROC,0x8,0x4,0x01,"Firefox(825,925)"},
31 {HPHW_NPROC,0xA,0x4,0x01,"Top Gun (835,834,935,635)"},
32 {HPHW_NPROC,0xB,0x4,0x01,"Technical Shogun (845, 645)"},
33 {HPHW_NPROC,0xF,0x4,0x01,"Commercial Shogun (949)"},
34 {HPHW_NPROC,0xC,0x4,0x01,"Cheetah (850, 950)"},
35 {HPHW_NPROC,0x80,0x4,0x01,"Cheetah (950S)"},
36 {HPHW_NPROC,0x81,0x4,0x01,"Jaguar (855, 955)"},
37 {HPHW_NPROC,0x82,0x4,0x01,"Cougar (860, 960)"},
38 {HPHW_NPROC,0x83,0x4,0x13,"Panther (865, 870, 980)"},
[all …]
/linux/drivers/pinctrl/nuvoton/
H A Dpinctrl-ma35d1.c26 MA35_PIN(1, PA1, 0x80, 0x4,
78 MA35_PIN(9, PA9, 0x84, 0x4,
115 MA35_MUX(0x4, "USBHL3_DM"),
124 MA35_MUX(0x4, "I2C4_SDA"),
135 MA35_PIN(17, PB1, 0x88, 0x4,
161 MA35_MUX(0x4, "I2C2_SDA"),
169 MA35_PIN(25, PB9, 0x8c, 0x4,
174 MA35_MUX(0x4, "I2C2_SCL"),
191 MA35_MUX(0x4, "USBHL2_DM"),
207 MA35_MUX(0x4, "USBHL2_DP"),
[all …]
/linux/drivers/media/usb/dvb-usb/
H A Daf9005-script.h25 {0xa0c0, 0x0, 0x4, 0x1},
26 {0xa20e, 0x4, 0x4, 0xa},
29 {0xa32a, 0x0, 0x4, 0xa},
39 {0xa00f, 0x0, 0x3, 0x4},
41 {0xa010, 0x0, 0x3, 0x4},
43 {0xa016, 0x4, 0x4, 0x3},
83 {0xa60e, 0x4, 0x2, 0x2},
106 {0xa60c, 0x0, 0x4, 0x5},
107 {0xa60c, 0x4, 0x4, 0x6},
115 {0xa33c, 0x3, 0x5, 0x4},
[all …]
/linux/drivers/net/wireless/mediatek/mt76/
H A Dmt792x_dma.c107 mt76_wr(dev, MT_WFDMA0_TX_RING0_EXT_CTRL, 0x4); in mt792x_dma_alloc_queues()
160 mt76_wr(dev, MT_WFDMA0_RX_RING0_EXT_CTRL, PREFETCH(0x0000, 0x4)); in mt7925_dma_prefetch_setup()
161 mt76_wr(dev, MT_WFDMA0_RX_RING1_EXT_CTRL, PREFETCH(0x0040, 0x4)); in mt7925_dma_prefetch_setup()
162 mt76_wr(dev, MT_WFDMA0_RX_RING2_EXT_CTRL, PREFETCH(0x0080, 0x4)); in mt7925_dma_prefetch_setup()
163 mt76_wr(dev, MT_WFDMA0_RX_RING3_EXT_CTRL, PREFETCH(0x00c0, 0x4)); in mt7925_dma_prefetch_setup()
170 mt76_wr(dev, MT_WFDMA0_TX_RING15_EXT_CTRL, PREFETCH(0x0500, 0x4)); in mt7925_dma_prefetch_setup()
171 mt76_wr(dev, MT_WFDMA0_TX_RING16_EXT_CTRL, PREFETCH(0x0540, 0x4)); in mt7925_dma_prefetch_setup()
191 mt76_wr(dev, MT_WFDMA0_RX_RING7_EXT_CTRL, PREFETCH(0x0100, 0x4)); in mt7927_dma_prefetch_setup()
192 mt76_wr(dev, MT_WFDMA0_TX_RING16_EXT_CTRL, PREFETCH(0x0140, 0x4)); in mt7927_dma_prefetch_setup()
194 mt76_wr(dev, MT_WFDMA0_TX_RING0_EXT_CTRL, PREFETCH(0x0280, 0x4)); in mt7927_dma_prefetch_setup()
[all …]
/linux/arch/powerpc/boot/dts/
H A Dkatmai.dts74 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
86 interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
98 interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
122 ranges = <0x4 0x00100000 0x4 0x00100000 0x00001000
123 0x4 0x00200000 0x4 0x00200000 0x00000400
124 0x4 0xe0000000 0x4 0xe0000000 0x20000000
145 interrupts = <0x0 0x1 0x2 0x3 0x4>;
149 interrupt-map = </*TXEOB*/ 0x0 &UIC1 0x6 0x4
150 /*RXEOB*/ 0x1 &UIC1 0x7 0x4
151 /*SERR*/ 0x2 &UIC1 0x1 0x4
[all …]
H A Dtaishan.dts73 interrupts = <0x1 0x4 0x0 0x4>; /* cascade - first non-critical */
86 interrupts = <0x3 0x4 0x2 0x4>; /* cascade */
98 interrupts = <0x5 0x4 0x4 0x4>; /* cascade */
149 interrupts = <0x0 0x1 0x2 0x3 0x4>;
153 interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4
154 /*RXEOB*/ 0x1 &UIC0 0xb 0x4
155 /*SERR*/ 0x2 &UIC1 0x0 0x4
156 /*TXDE*/ 0x3 &UIC1 0x1 0x4
157 /*RXDE*/ 0x4 &UIC1 0x2 0x4>;
171 interrupts = <0x7 0x4>;
[all …]
H A Dicon.dts70 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
82 interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
94 interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
118 ranges = <0x4 0x00100000 0x4 0x00100000 0x00001000
119 0x4 0x00200000 0x4 0x00200000 0x00000400
120 0x4 0xe0000000 0x4 0xe0000000 0x20000000
141 interrupts = <0x0 0x1 0x2 0x3 0x4>;
145 interrupt-map = </*TXEOB*/ 0x0 &UIC1 0x6 0x4
146 /*RXEOB*/ 0x1 &UIC1 0x7 0x4
147 /*SERR*/ 0x2 &UIC1 0x1 0x4
[all …]
/linux/arch/powerpc/boot/dts/fsl/
H A Dmpc8568mds.dts30 0x4 0x0 0xf8008000 0x00008000
128 0x4 0xa 0x1 0x0 0x2 0x0 /* TxD0 */
129 0x4 0x9 0x1 0x0 0x2 0x0 /* TxD1 */
130 0x4 0x8 0x1 0x0 0x2 0x0 /* TxD2 */
131 0x4 0x7 0x1 0x0 0x2 0x0 /* TxD3 */
132 0x4 0x17 0x1 0x0 0x2 0x0 /* TxD4 */
133 0x4 0x16 0x1 0x0 0x2 0x0 /* TxD5 */
134 0x4 0x15 0x1 0x0 0x2 0x0 /* TxD6 */
135 0x4 0x14 0x1 0x0 0x2 0x0 /* TxD7 */
136 0x4 0xf 0x2 0x0 0x2 0x0 /* RxD0 */
[all …]
H A Dmpc8572ds.dtsi131 reg = <0x4 0x0 0x40000>;
252 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
253 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
258 0x8900 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
259 0x8900 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
264 0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
265 0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
270 0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
271 0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
276 0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
[all …]
/linux/arch/arm/boot/dts/st/
H A Dspear1310.dtsi56 interrupts = <0 68 0x4>;
65 interrupts = <0 69 0x4>;
74 interrupts = <0 70 0x4>;
84 interrupts = <0 68 0x4>;
101 interrupts = <0 69 0x4>;
118 interrupts = <0 70 0x4>;
134 interrupts = <0 95 0x4>;
143 interrupts = <0 96 0x4>;
152 interrupts = <0 97 0x4>;
161 interrupts = <0 98 0x4>;
[all …]

12345678910>>...108