Home
last modified time | relevance | path

Searched full:x3 (Results 1 – 25 of 2999) sorted by relevance

12345678910>>...120

/linux/arch/x86/crypto/
H A Dserpent-avx-x86_64-asm_64.S51 #define S0_1(x0, x1, x2, x3, x4) \ argument
52 vpor x0, x3, tp; \
53 vpxor x3, x0, x0; \
54 vpxor x2, x3, x4; \
56 vpxor x1, tp, x3; \
60 #define S0_2(x0, x1, x2, x3, x4) \ argument
61 vpxor x3, x0, x0; \
65 vpxor x2, x3, x3; \
70 #define S1_1(x0, x1, x2, x3, x4) \ argument
72 vpxor x3, x0, x0; \
[all …]
H A Dserpent-avx2-asm_64.S51 #define S0_1(x0, x1, x2, x3, x4) \ argument
52 vpor x0, x3, tp; \
53 vpxor x3, x0, x0; \
54 vpxor x2, x3, x4; \
56 vpxor x1, tp, x3; \
60 #define S0_2(x0, x1, x2, x3, x4) \ argument
61 vpxor x3, x0, x0; \
65 vpxor x2, x3, x3; \
70 #define S1_1(x0, x1, x2, x3, x4) \ argument
72 vpxor x3, x0, x0; \
[all …]
H A Dserpent-sse2-i586-asm_32.S42 #define K(x0, x1, x2, x3, x4, i) \ argument
50 pxor x4, x3;
52 #define LK(x0, x1, x2, x3, x4, i) \ argument
69 pxor x2, x3; \
70 pxor x4, x3; \
71 movdqa x3, x4; \
72 pslld $7, x3; \
74 por x4, x3; \
78 pxor x3, x0; \
79 pxor x3, x2; \
[all …]
H A Dserpent-sse2-x86_64-asm_64.S41 #define S0_1(x0, x1, x2, x3, x4) \ argument
42 movdqa x3, x4; \
43 por x0, x3; \
47 pxor x1, x3; \
51 #define S0_2(x0, x1, x2, x3, x4) \ argument
52 pxor x3, x0; \
56 pxor x2, x3; \
61 #define S1_1(x0, x1, x2, x3, x4) \ argument
64 pxor x3, x0; \
65 pxor RNOT, x3; \
[all …]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-serdes.h16 #define J721E_SERDES0_LANE0_IP4_UNUSED 0x3
21 #define J721E_SERDES0_LANE1_IP4_UNUSED 0x3
26 #define J721E_SERDES1_LANE0_SGMII_LANE0 0x3
31 #define J721E_SERDES1_LANE1_SGMII_LANE1 0x3
36 #define J721E_SERDES2_LANE0_SGMII_LANE0 0x3
41 #define J721E_SERDES2_LANE1_SGMII_LANE1 0x3
46 #define J721E_SERDES3_LANE0_IP4_UNUSED 0x3
51 #define J721E_SERDES3_LANE1_IP4_UNUSED 0x3
56 #define J721E_SERDES4_LANE0_IP4_UNUSED 0x3
61 #define J721E_SERDES4_LANE1_IP4_UNUSED 0x3
[all …]
/linux/drivers/pinctrl/berlin/
H A Dberlin-bg4ct.c19 BERLIN_PINCTRL_GROUP("EMMC_RSTn", 0x0, 0x3, 0x00,
22 BERLIN_PINCTRL_GROUP("NAND_IO0", 0x0, 0x3, 0x03,
26 BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO0 */
27 BERLIN_PINCTRL_GROUP("NAND_IO1", 0x0, 0x3, 0x06,
31 BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO1 */
32 BERLIN_PINCTRL_GROUP("NAND_IO2", 0x0, 0x3, 0x09,
36 BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO2 */
37 BERLIN_PINCTRL_GROUP("NAND_IO3", 0x0, 0x3, 0x0c,
41 BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO3 */
42 BERLIN_PINCTRL_GROUP("NAND_IO4", 0x0, 0x3, 0x0f,
[all …]
H A Dpinctrl-as370.c19 BERLIN_PINCTRL_GROUP("I2S1_BCLKIO", 0x0, 0x3, 0x00,
23 BERLIN_PINCTRL_GROUP("I2S1_LRCKIO", 0x0, 0x3, 0x03,
27 BERLIN_PINCTRL_GROUP("I2S1_DO0", 0x0, 0x3, 0x06,
30 BERLIN_PINCTRL_FUNCTION(0x3, "gpio"), /* GPIO2 */
32 BERLIN_PINCTRL_GROUP("I2S1_DO1", 0x0, 0x3, 0x09,
35 BERLIN_PINCTRL_FUNCTION(0x3, "gpio"), /* GPIO3 */
37 BERLIN_PINCTRL_GROUP("I2S1_DO2", 0x0, 0x3, 0x0c,
41 BERLIN_PINCTRL_FUNCTION(0x3, "gpio"), /* GPIO4 */
43 BERLIN_PINCTRL_GROUP("I2S1_DO3", 0x0, 0x3, 0x0f,
47 BERLIN_PINCTRL_FUNCTION(0x3, "spdifib"), /* SPDIFIB */
[all …]
H A Dberlin-bg2q.c20 BERLIN_PINCTRL_GROUP("G0", 0x18, 0x3, 0x00,
24 BERLIN_PINCTRL_GROUP("G1", 0x18, 0x3, 0x03,
27 BERLIN_PINCTRL_GROUP("G2", 0x18, 0x3, 0x06,
30 BERLIN_PINCTRL_FUNCTION(0x3, "lvds")),
31 BERLIN_PINCTRL_GROUP("G3", 0x18, 0x3, 0x09,
34 BERLIN_PINCTRL_FUNCTION(0x3, "lvds")),
35 BERLIN_PINCTRL_GROUP("G4", 0x18, 0x3, 0x0c,
39 BERLIN_PINCTRL_FUNCTION(0x3, "gpio"),
43 BERLIN_PINCTRL_GROUP("G5", 0x18, 0x3, 0x0f,
50 BERLIN_PINCTRL_GROUP("G6", 0x18, 0x3, 0x12,
[all …]
H A Dberlin-bg2cd.c20 BERLIN_PINCTRL_GROUP("G0", 0x00, 0x3, 0x00,
24 BERLIN_PINCTRL_FUNCTION(0x3, "pwm")),
25 BERLIN_PINCTRL_GROUP("G1", 0x00, 0x3, 0x03,
30 BERLIN_PINCTRL_GROUP("G2", 0x00, 0x3, 0x06,
34 BERLIN_PINCTRL_FUNCTION(0x3, "pll"),
37 BERLIN_PINCTRL_GROUP("G3", 0x00, 0x3, 0x09,
41 BERLIN_PINCTRL_FUNCTION(0x3, "pll"),
45 BERLIN_PINCTRL_GROUP("G4", 0x00, 0x3, 0x0c,
49 BERLIN_PINCTRL_FUNCTION(0x3, "pll"),
53 BERLIN_PINCTRL_GROUP("G5", 0x00, 0x3, 0x0f,
[all …]
/linux/include/dt-bindings/mux/
H A Dti-serdes.h22 #define J721E_SERDES0_LANE0_IP4_UNUSED 0x3
27 #define J721E_SERDES0_LANE1_IP4_UNUSED 0x3
32 #define J721E_SERDES1_LANE0_SGMII_LANE0 0x3
37 #define J721E_SERDES1_LANE1_SGMII_LANE1 0x3
42 #define J721E_SERDES2_LANE0_SGMII_LANE0 0x3
47 #define J721E_SERDES2_LANE1_SGMII_LANE1 0x3
52 #define J721E_SERDES3_LANE0_IP4_UNUSED 0x3
57 #define J721E_SERDES3_LANE1_IP4_UNUSED 0x3
62 #define J721E_SERDES4_LANE0_IP4_UNUSED 0x3
67 #define J721E_SERDES4_LANE1_IP4_UNUSED 0x3
[all …]
/linux/crypto/
H A Dserpent_generic.c27 #define loadkeys(x0, x1, x2, x3, i) \ argument
28 ({ x0 = k[i]; x1 = k[i+1]; x2 = k[i+2]; x3 = k[i+3]; })
30 #define storekeys(x0, x1, x2, x3, i) \ argument
31 ({ k[i] = x0; k[i+1] = x1; k[i+2] = x2; k[i+3] = x3; })
33 #define store_and_load_keys(x0, x1, x2, x3, s, l) \ argument
34 ({ storekeys(x0, x1, x2, x3, s); loadkeys(x0, x1, x2, x3, l); })
36 #define K(x0, x1, x2, x3, i) ({ \ argument
37 x3 ^= k[4*(i)+3]; x2 ^= k[4*(i)+2]; \
41 #define LK(x0, x1, x2, x3, x4, i) ({ \ argument
44 x3 ^= x2; x1 ^= x2; \
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx7ulp-pinfunc.h41 #define IMX7ULP_PAD_PTC4__LPSPI2_PCS1 0x0010 0x02a0 0x3 0x1
49 #define IMX7ULP_PAD_PTC5__LPSPI2_PCS2 0x0014 0x02a4 0x3 0x1
57 #define IMX7ULP_PAD_PTC6__LPSPI2_PCS3 0x0018 0x02a8 0x3 0x1
71 #define IMX7ULP_PAD_PTC8__LPSPI2_SIN 0x0020 0x02b0 0x3 0x1
79 #define IMX7ULP_PAD_PTC9__LPSPI2_SOUT 0x0024 0x02b4 0x3 0x1
87 #define IMX7ULP_PAD_PTC10__LPSPI2_SCK 0x0028 0x02ac 0x3 0x1
95 #define IMX7ULP_PAD_PTC11__LPSPI2_PCS0 0x002c 0x029c 0x3 0x1
102 #define IMX7ULP_PAD_PTC12__LPSPI3_PCS1 0x0030 0x0314 0x3 0x1
110 #define IMX7ULP_PAD_PTC13__LPSPI3_PCS2 0x0034 0x0318 0x3 0x1
119 #define IMX7ULP_PAD_PTC14__LPSPI3_PCS3 0x0038 0x031c 0x3 0x1
[all …]
H A Dimx7d-pinfunc.h17 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0
22 #define MX7D_PAD_LPSR_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0
27 #define MX7D_PAD_LPSR_GPIO1_IO02__CCM_ENET_REF_CLK1 0x0008 0x0038 0x0564 0x2 0x3
28 #define MX7D_PAD_LPSR_GPIO1_IO02__SAI2_MCLK 0x0008 0x0038 0x0000 0x3 0x0
31 #define MX7D_PAD_LPSR_GPIO1_IO02__USB_OTG1_ID 0x0008 0x0038 0x0734 0x7 0x3
34 #define MX7D_PAD_LPSR_GPIO1_IO03__CCM_ENET_REF_CLK2 0x000C 0x003C 0x0570 0x2 0x3
35 #define MX7D_PAD_LPSR_GPIO1_IO03__SAI3_MCLK 0x000C 0x003C 0x0000 0x3 0x0
38 #define MX7D_PAD_LPSR_GPIO1_IO03__USB_OTG2_ID 0x000C 0x003C 0x0730 0x7 0x3
42 #define MX7D_PAD_LPSR_GPIO1_IO04__UART5_DCE_CTS 0x0010 0x0040 0x0000 0x3 0x0
43 #define MX7D_PAD_LPSR_GPIO1_IO04__UART5_DTE_RTS 0x0010 0x0040 0x0710 0x3 0x4
[all …]
H A Dimxrt1050-pinfunc.h20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0
27 #define MXRT1050_IOMUXC_GPIO_EMC_01_XBAR_INOUT3 0x018 0x208 0x610 0x3 0x0
34 #define MXRT1050_IOMUXC_GPIO_EMC_02_XBAR_INOUT4 0x01C 0x20C 0x614 0x3 0x0
41 #define MXRT1050_IOMUXC_GPIO_EMC_03_XBAR_INOUT5 0x020 0x210 0x618 0x3 0x0
48 #define MXRT1050_IOMUXC_GPIO_EMC_04_XBAR_INOUT6 0x024 0x214 0x61C 0x3 0x0
55 #define MXRT1050_IOMUXC_GPIO_EMC_05_XBAR_INOUT7 0x028 0x218 0x620 0x3 0x0
62 #define MXRT1050_IOMUXC_GPIO_EMC_06_XBAR_INOUT8 0x02C 0x21C 0x624 0x3 0x0
69 #define MXRT1050_IOMUXC_GPIO_EMC_07_XBAR_INOUT9 0x030 0x220 0x628 0x3 0x0
76 #define MXRT1050_IOMUXC_GPIO_EMC_08_XBAR_INOUT17 0x034 0x224 0x62C 0x3 0x0
83 #define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXCAN2_TX 0x038 0x228 0x000 0x3 0x0
[all …]
H A Dimx6sl-pinfunc.h16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
24 #define MX6SL_PAD_AUD_RXC__FEC_TX_CLK 0x050 0x2a8 0x70c 0x3 0x0
32 #define MX6SL_PAD_AUD_RXD__FEC_RX_ER 0x054 0x2ac 0x708 0x3 0x0
39 #define MX6SL_PAD_AUD_RXFS__FEC_MDIO 0x058 0x2b0 0x6f4 0x3 0x0
47 #define MX6SL_PAD_AUD_TXC__FEC_RX_DV 0x05c 0x2b4 0x704 0x3 0x0
54 #define MX6SL_PAD_AUD_TXD__FEC_TX_DATA0 0x060 0x2b8 0x000 0x3 0x0
61 #define MX6SL_PAD_AUD_TXFS__FEC_RX_DATA1 0x064 0x2bc 0x6fc 0x3 0x0
68 #define MX6SL_PAD_ECSPI1_MISO__EPDC_BDR0 0x068 0x358 0x000 0x3 0x0
75 #define MX6SL_PAD_ECSPI1_MOSI__EPDC_VCOM1 0x06c 0x35c 0x000 0x3 0x0
82 #define MX6SL_PAD_ECSPI1_SCLK__EPDC_VCOM0 0x070 0x360 0x000 0x3 0x0
[all …]
H A Dimx51-pinfunc.h18 #define MX51_PAD_EIM_D16__UART2_CTS 0x05c 0x3f0 0x000 0x3 0x0
23 #define MX51_PAD_EIM_D17__UART2_RXD 0x060 0x3f4 0x9ec 0x3 0x0
29 #define MX51_PAD_EIM_D18__UART2_TXD 0x064 0x3f8 0x000 0x3 0x0
37 #define MX51_PAD_EIM_D19__UART2_RTS 0x068 0x3fc 0x9e8 0x3 0x1
47 #define MX51_PAD_EIM_D21__SRTC_ALARM_DEB 0x070 0x404 0x000 0x3 0x0
62 #define MX51_PAD_EIM_D24__UART3_CTS 0x07c 0x410 0x000 0x3 0x0
67 #define MX51_PAD_EIM_D25__UART3_RXD 0x080 0x414 0x9f4 0x3 0x0
71 #define MX51_PAD_EIM_D26__UART2_RTS 0x084 0x418 0x9e8 0x4 0x3
72 #define MX51_PAD_EIM_D26__UART3_TXD 0x084 0x418 0x000 0x3 0x0
78 #define MX51_PAD_EIM_D27__UART3_RTS 0x088 0x41c 0x9f0 0x3 0x3
[all …]
H A Dimx53-pinfunc.h16 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0
65 #define MX53_PAD_KEY_COL3__SPDIF_IN1 0x03c 0x364 0x870 0x3 0x0
73 #define MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK 0x040 0x368 0x768 0x3 0x0
81 #define MX53_PAD_KEY_COL4__IPU_SISG_4 0x044 0x36c 0x000 0x3 0x0
88 #define MX53_PAD_KEY_ROW4__IPU_SISG_5 0x048 0x370 0x000 0x3 0x0
119 #define MX53_PAD_DI0_PIN4__ESDHC1_WP 0x05c 0x388 0x7fc 0x3 0x0
126 #define MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 0x060 0x38c 0x000 0x3 0x0
133 #define MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 0x064 0x390 0x000 0x3 0x0
140 #define MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 0x068 0x394 0x000 0x3 0x0
147 #define MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 0x06c 0x398 0x000 0x3 0x0
[all …]
/linux/arch/arm64/lib/
H A Dtishift.S12 mov x3, #64
13 sub x3, x3, x2
14 cmp x3, #0
17 lsr x3, x0, x3
19 orr x1, x1, x3
34 mov x3, #64
35 sub x3, x3, x2
36 cmp x3, #0
39 lsl x3, x1, x3
41 orr x0, x0, x3
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mp-pinfunc.h15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0
19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0
23 #define MX8MP_IOMUXC_GPIO1_IO02__ISP_FLASH_TRIG_0 0x01C 0x27C 0x000 0x3 0x0
28 #define MX8MP_IOMUXC_GPIO1_IO03__ISP_PRELIGHT_TRIG_0 0x020 0x280 0x000 0x3 0x0
32 #define MX8MP_IOMUXC_GPIO1_IO04__ISP_SHUTTER_OPEN_0 0x024 0x284 0x000 0x3 0x0
36 #define MX8MP_IOMUXC_GPIO1_IO05__ISP_FL_TRIG_1 0x028 0x288 0x5D8 0x3 0x0
40 #define MX8MP_IOMUXC_GPIO1_IO06__ISP_SHUTTER_TRIG_1 0x02C 0x28C 0x5E0 0x3 0x0
45 #define MX8MP_IOMUXC_GPIO1_IO07__ISP_FLASH_TRIG_1 0x030 0x290 0x000 0x3 0x0
51 #define MX8MP_IOMUXC_GPIO1_IO08__ISP_PRELIGHT_TRIG_1 0x034 0x294 0x000 0x3 0x0
57 #define MX8MP_IOMUXC_GPIO1_IO09__ISP_SHUTTER_OPEN_1 0x038 0x298 0x000 0x3 0x0
[all …]
/linux/drivers/pinctrl/sunxi/
H A Dpinctrl-sun4i-a10.c25 SUNXI_FUNCTION(0x3, "spi1"), /* CS0 */
34 SUNXI_FUNCTION(0x3, "spi1"), /* CLK */
43 SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */
52 SUNXI_FUNCTION(0x3, "spi1"), /* MISO */
61 SUNXI_FUNCTION(0x3, "spi1"), /* CS1 */
69 SUNXI_FUNCTION(0x3, "spi3"), /* CS0 */
77 SUNXI_FUNCTION(0x3, "spi3"), /* CLK */
85 SUNXI_FUNCTION(0x3, "spi3"), /* MOSI */
93 SUNXI_FUNCTION(0x3, "spi3"), /* MISO */
101 SUNXI_FUNCTION(0x3, "spi3"), /* CS1 */
[all …]
/linux/drivers/net/ethernet/qlogic/qed/
H A Dqed_hsi.h147 #define CORE_PWM_PROD_UPDATE_DATA_AGG_CMD_MASK 0x3
188 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_MASK 0x3
190 #define CORE_RX_ACTION_ON_ERROR_NO_BUFF_MASK 0x3
359 #define CORE_TX_BD_TX_DST_MASK 0x3
469 #define XSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
471 #define XSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
473 #define XSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
475 #define XSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3
478 #define XSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3
480 #define XSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3
[all …]
/linux/include/linux/mfd/syscon/
H A Dimx6q-iomuxc-gpr.h26 #define IMX6Q_GPR0_CLOCK_8_MUX_SEL_MASK (0x3 << 30)
30 #define IMX6Q_GPR0_CLOCK_8_MUX_SEL_SSI3_RX_BIT_CLK (0x3 << 30)
31 #define IMX6Q_GPR0_CLOCK_0_MUX_SEL_MASK (0x3 << 28)
35 #define IMX6Q_GPR0_CLOCK_B_MUX_SEL_MASK (0x3 << 26)
39 #define IMX6Q_GPR0_CLOCK_B_MUX_SEL_SSI3_TX_BIT_CLK (0x3 << 26)
40 #define IMX6Q_GPR0_CLOCK_3_MUX_SEL_MASK (0x3 << 24)
41 #define IMX6Q_GPR0_CLOCK_3_MUX_SEL_AUDMUX_RXCLK_P7_MUXED (0x3 << 24)
42 #define IMX6Q_GPR0_CLOCK_3_MUX_SEL_AUDMUX_RXCLK_P7 (0x3 << 24)
43 #define IMX6Q_GPR0_CLOCK_3_MUX_SEL_SSI3_SSI_SRCK (0x3 << 24)
44 #define IMX6Q_GPR0_CLOCK_3_MUX_SEL_SSI3_RX_BIT_CLK (0x3 << 24)
[all …]
/linux/drivers/clk/mmp/
H A Dclk-of-pxa1928.c108 …{PXA1928_CLK_TWSI0, "twsi0_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI0 * 4, 0x3, 0x3, 0…
109 …{PXA1928_CLK_TWSI1, "twsi1_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI1 * 4, 0x3, 0x3, 0…
110 …{PXA1928_CLK_TWSI2, "twsi2_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI2 * 4, 0x3, 0x3, 0…
111 …{PXA1928_CLK_TWSI3, "twsi3_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI3 * 4, 0x3, 0x3, 0…
112 …{PXA1928_CLK_TWSI4, "twsi4_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI4 * 4, 0x3, 0x3, 0…
113 …{PXA1928_CLK_TWSI5, "twsi5_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI5 * 4, 0x3, 0x3, 0…
114 …{PXA1928_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_GPIO * 4, 0x3, 0x3, 0x0,…
115 …{PXA1928_CLK_KPC, "kpc_clk", "clk32", CLK_SET_RATE_PARENT, PXA1928_CLK_KPC * 4, 0x3, 0x3, 0x0, MMP…
117 …{PXA1928_CLK_PWM0, "pwm0_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_PWM0 * 4, 0x3, 0x3, 0x0,…
118 …{PXA1928_CLK_PWM1, "pwm1_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_PWM1 * 4, 0x3, 0x3, 0x0,…
[all …]
/linux/drivers/net/wireless/mediatek/mt76/mt76x0/
H A Dinitvals_phy.h321 …x3F, 0x28, 0xDD, 0xE2, 0x40, 0x02, 0x40, 0x02, 0, 0, 1, 0x28, 0, 0x30, 0, 0, 0x3 }, /* Freq 2412 */
327 …x3F, 0x28, 0xDD, 0xE2, 0x40, 0x02, 0x40, 0x07, 0, 0, 1, 0x28, 0, 0x30, 0, 0, 0x3 }, /* Freq 2442 */
329 …x3F, 0x3C, 0xDD, 0xF2, 0x40, 0x07, 0x40, 0x0D, 0, 0, 1, 0x28, 0, 0x30, 0, 0, 0x3 }, /* Freq 2452 */
333 …x3F, 0x28, 0xDD, 0xF2, 0x40, 0x02, 0x40, 0x02, 0, 0, 1, 0x29, 0, 0x30, 0, 0, 0x3 }, /* Freq 2472 */
334 …x3F, 0x28, 0xDD, 0xF2, 0x40, 0x02, 0x40, 0x04, 0, 0, 1, 0x29, 0, 0x30, 0, 0, 0x3 }, /* Freq 2484 */
335 …x3F, 0x70, 0xDD, 0xD2, 0x40, 0x10, 0x40, 0x17, 0, 0, 1, 0x28, 0, 0x30, 0, 0, 0x3 }, /* Freq 4915 */
336 …x3F, 0x68, 0xDD, 0xD2, 0x40, 0x10, 0x40, 0x00, 0, 0, 1, 0x29, 0, 0x30, 0, 0, 0x3 }, /* Freq 4920 */
337 …x3F, 0x68, 0xDD, 0xD2, 0x40, 0x10, 0x40, 0x01, 0, 0, 1, 0x29, 0, 0x30, 0, 0, 0x3 }, /* Freq 4925 */
338 …x3F, 0x68, 0xDD, 0xD2, 0x40, 0x10, 0x40, 0x03, 0, 0, 1, 0x29, 0, 0x30, 0, 0, 0x3 }, /* Freq 4935 */
339 …x3F, 0x30, 0x97, 0xD2, 0x40, 0x04, 0x40, 0x02, 0, 0, 1, 0x29, 0, 0x30, 0, 0, 0x3 }, /* Freq 4940 */
[all …]
/linux/arch/arm/mach-omap2/
H A Dprm-regbits-33xx.h13 #define AM33XX_GFX_MEM_ONSTATE_MASK (0x3 << 17)
15 #define AM33XX_GFX_MEM_STATEST_MASK (0x3 << 4)
19 #define AM33XX_PRUSS_MEM_ONSTATE_MASK (0x3 << 5)
21 #define AM33XX_PRUSS_MEM_STATEST_MASK (0x3 << 23)
23 #define AM33XX_LASTPOWERSTATEENTERED_MASK (0x3 << 24)
30 #define AM33XX_MPU_L1_ONSTATE_MASK (0x3 << 18)
32 #define AM33XX_MPU_L1_STATEST_MASK (0x3 << 6)
33 #define AM33XX_MPU_L2_ONSTATE_MASK (0x3 << 20)
35 #define AM33XX_MPU_L2_STATEST_MASK (0x3 << 8)
36 #define AM33XX_MPU_RAM_ONSTATE_MASK (0x3 << 16)
[all …]

12345678910>>...120