Searched +full:x1e80100 +full:- +full:cpucp +full:- +full:mbox (Results 1 – 3 of 3) sorted by relevance
| /linux/Documentation/devicetree/bindings/mailbox/ |
| H A D | qcom,cpucp-mbox.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mailbox/qcom,cpucp-mbox.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies, Inc. CPUCP Mailbox Controller
10 - Sibi Sankar <quic_sibis@quicinc.com>
13 The CPUSS Control Processor (CPUCP) mailbox controller enables communication
14 between AP and CPUCP by acting as a doorbell between them.
19 - const: qcom,x1e80100-cpucp-mbox
23 - description: CPUCP rx register region
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| /linux/drivers/mailbox/ |
| H A D | qcom-cpucp-mbox.c | 1 // SPDX-License-Identifier: GPL-2.0-only
30 * struct qcom_cpucp_mbox - Holder for the mailbox driver
32 * @mbox: The mailbox controller
33 * @tx_base: Base address of the CPUCP tx registers
34 * @rx_base: Base address of the CPUCP rx registers
38 struct mbox_controller mbox; member
45 return chan - chan->mbox->chans; in channel_number()
50 struct qcom_cpucp_mbox *cpucp = data; in qcom_cpucp_mbox_irq_fn() local
54 status = readq(cpucp->rx_base + APSS_CPUCP_RX_MBOX_STAT); in qcom_cpucp_mbox_irq_fn()
57 u32 val = readl(cpucp->rx_base + APSS_CPUCP_RX_MBOX_CMD(i) + APSS_CPUCP_MBOX_CMD_OFF); in qcom_cpucp_mbox_irq_fn()
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| /linux/arch/arm64/boot/dts/qcom/ |
| H A D | x1e80100.dtsi | 1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
8 #include <dt-bindings/clock/qcom,x1e80100-dispcc.h>
9 #include <dt-bindings/clock/qcom,x1e80100-gcc.h>
10 #include <dt-bindings/clock/qcom,x1e80100-gpucc.h>
11 #include <dt-bindings/clock/qcom,x1e80100-tcsr.h>
12 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/interconnect/qcom,icc.h>
14 #include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h>
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