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/linux/drivers/gpu/drm/msm/adreno/
H A Da6xx_gpu_state.h404 REG_A6XX_CP_DRAW_STATE_DATA, 0x100, NULL },
415 REG_A6XX_CP_DRAW_STATE_DATA, 0x100, NULL },
421 REG_A7XX_CP_BV_DRAW_STATE_DATA, 0x100, NULL },
427 REG_A7XX_CP_LPAC_DRAW_STATE_DATA, 0x100, NULL },
455 DEBUGBUS(A6XX_DBGBUS_CP, 0x100),
456 DEBUGBUS(A6XX_DBGBUS_RBBM, 0x100),
457 DEBUGBUS(A6XX_DBGBUS_HLSQ, 0x100),
458 DEBUGBUS(A6XX_DBGBUS_UCHE, 0x100),
459 DEBUGBUS(A6XX_DBGBUS_DPM, 0x100),
460 DEBUGBUS(A6XX_DBGBUS_TESS, 0x100),
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dmscc,vsc7514-switch.yaml134 <0x1080000 0x100>,
136 <0x11e0000 0x100>,
137 <0x11f0000 0x100>,
138 <0x1200000 0x100>,
139 <0x1210000 0x100>,
140 <0x1220000 0x100>,
141 <0x1230000 0x100>,
142 <0x1240000 0x100>,
143 <0x1250000 0x100>,
144 <0x1260000 0x100>,
[all …]
/linux/drivers/gpu/drm/radeon/
H A Drv770.c188 0x5448, 0xffffffff, 0x100,
189 0x55e4, 0xffffffff, 0x100,
190 0x160c, 0xffffffff, 0x100,
191 0x5644, 0xffffffff, 0x100,
192 0xc164, 0xffffffff, 0x100,
193 0x8a18, 0xffffffff, 0x100,
196 0x9144, 0xffffffff, 0x100,
198 0x9a50, 0xffffffff, 0x100,
200 0x9a50, 0xffffffff, 0x100,
202 0x9a50, 0xffffffff, 0x100,
[all …]
/linux/drivers/net/ethernet/intel/igbvf/
H A Dregs.h27 #define E1000_RDBAL(_n) ((_n) < 4 ? (0x02800 + ((_n) * 0x100)) : \
29 #define E1000_RDBAH(_n) ((_n) < 4 ? (0x02804 + ((_n) * 0x100)) : \
31 #define E1000_RDLEN(_n) ((_n) < 4 ? (0x02808 + ((_n) * 0x100)) : \
33 #define E1000_SRRCTL(_n) ((_n) < 4 ? (0x0280C + ((_n) * 0x100)) : \
35 #define E1000_RDH(_n) ((_n) < 4 ? (0x02810 + ((_n) * 0x100)) : \
37 #define E1000_RDT(_n) ((_n) < 4 ? (0x02818 + ((_n) * 0x100)) : \
39 #define E1000_RXDCTL(_n) ((_n) < 4 ? (0x02828 + ((_n) * 0x100)) : \
41 #define E1000_TDBAL(_n) ((_n) < 4 ? (0x03800 + ((_n) * 0x100)) : \
43 #define E1000_TDBAH(_n) ((_n) < 4 ? (0x03804 + ((_n) * 0x100)) : \
45 #define E1000_TDLEN(_n) ((_n) < 4 ? (0x03808 + ((_n) * 0x100)) : \
[all …]
/linux/arch/powerpc/boot/dts/
H A Dmpc5121.dtsi111 reg = <0xc00 0x100>;
117 reg = <0x900 0x100>;
123 reg = <0xa00 0x100>;
130 reg = <0xe00 0x100>;
136 reg = <0xf00 0x100>;
145 reg = <0x1000 0x100>;
151 reg = <0x1100 0x100>;
181 reg = <0x1500 0x100>;
227 reg = <0x2000 0x100>;
235 reg = <0x2100 0x100>;
[all …]
/linux/arch/mips/boot/dts/mscc/
H A Docelot.dtsi85 reg = <0x100400 0x100>, <0x198 0x8>;
111 reg = <0x101000 0x100>, <0x3c 0x18>;
122 <0x1080000 0x100>,
124 <0x11e0000 0x100>,
125 <0x11f0000 0x100>,
126 <0x1200000 0x100>,
127 <0x1210000 0x100>,
128 <0x1220000 0x100>,
129 <0x1230000 0x100>,
130 <0x1240000 0x100>,
[all …]
/linux/arch/arm64/boot/dts/nuvoton/
H A Dma35d1.dtsi93 reg = <0x00000000 0x40460200 0x0 0x100>;
147 reg = <0x100 0x40>;
249 reg = <0x0 0x40700000 0x0 0x100>;
257 reg = <0x0 0x40710000 0x0 0x100>;
265 reg = <0x0 0x40720000 0x0 0x100>;
273 reg = <0x0 0x40730000 0x0 0x100>;
281 reg = <0x0 0x40740000 0x0 0x100>;
289 reg = <0x0 0x40750000 0x0 0x100>;
297 reg = <0x0 0x40760000 0x0 0x100>;
305 reg = <0x0 0x40770000 0x0 0x100>;
[all …]
/linux/arch/mips/include/asm/mach-ralink/
H A Drt3883.h45 #define RT3883_SYSC_SIZE 0x100
46 #define RT3883_TIMER_SIZE 0x100
47 #define RT3883_INTC_SIZE 0x100
48 #define RT3883_MEMC_SIZE 0x100
49 #define RT3883_UART0_SIZE 0x100
50 #define RT3883_UART1_SIZE 0x100
51 #define RT3883_PIO_SIZE 0x100
52 #define RT3883_FSCC_SIZE 0x100
54 #define RT3883_I2C_SIZE 0x100
55 #define RT3883_I2S_SIZE 0x100
[all …]
/linux/Documentation/devicetree/bindings/remoteproc/
H A Dti,pru-rproc.yaml143 <0x22400 0x100>;
152 <0x24400 0x100>;
181 <0x22000 0x100>,
182 <0x22400 0x100>;
193 <0x23000 0x100>,
194 <0x23400 0x100>;
205 <0x25000 0x100>,
206 <0x25400 0x100>;
214 <0x24000 0x100>,
215 <0x24400 0x100>;
[all …]
/linux/arch/arm/boot/dts/samsung/
H A Dexynos5.dtsi40 reg = <0x10000000 0x100>;
107 reg = <0x12c00000 0x100>;
113 reg = <0x12c10000 0x100>;
119 reg = <0x12c20000 0x100>;
125 reg = <0x12c30000 0x100>;
131 reg = <0x12c60000 0x100>;
141 reg = <0x12c70000 0x100>;
151 reg = <0x12c80000 0x100>;
161 reg = <0x12c90000 0x100>;
171 reg = <0x12dd0000 0x100>;
[all …]
H A Dexynos4.dtsi79 reg = <0x03830000 0x100>;
95 reg = <0x10000000 0x100>;
300 reg = <0x10070000 0x100>;
311 reg = <0x100a0000 0x100>;
320 reg = <0x12510000 0x100>;
329 reg = <0x12520000 0x100>;
338 reg = <0x12530000 0x100>;
347 reg = <0x12540000 0x100>;
356 reg = <0x125b0000 0x100>;
377 reg = <0x12580000 0x100>;
[all …]
/linux/sound/soc/codecs/
H A Dwm8770.c64 { 27, 0x100 },
353 master = 0x100; in wm8770_set_fmt()
393 snd_soc_component_update_bits(component, WM8770_MSTRCTRL, 0x100, master); in wm8770_set_fmt()
450 if (snd_soc_component_read(component, WM8770_MSTRCTRL) & 0x100) { in wm8770_hw_params()
590 snd_soc_component_update_bits(component, WM8770_MSDIGVOL, 0x100, 0x100); in wm8770_probe()
591 snd_soc_component_update_bits(component, WM8770_MSALGVOL, 0x100, 0x100); in wm8770_probe()
592 snd_soc_component_update_bits(component, WM8770_VOUT1RVOL, 0x100, 0x100); in wm8770_probe()
593 snd_soc_component_update_bits(component, WM8770_VOUT2RVOL, 0x100, 0x100); in wm8770_probe()
594 snd_soc_component_update_bits(component, WM8770_VOUT3RVOL, 0x100, 0x100); in wm8770_probe()
595 snd_soc_component_update_bits(component, WM8770_VOUT4RVOL, 0x100, 0x100); in wm8770_probe()
[all …]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-am65-main.dtsi97 reg = <0x00 0x02800000 0x00 0x100>;
106 reg = <0x00 0x02810000 0x00 0x100>;
115 reg = <0x00 0x02820000 0x00 0x100>;
178 reg = <0x0 0x2000000 0x0 0x100>;
190 reg = <0x0 0x2010000 0x0 0x100>;
202 reg = <0x0 0x2020000 0x0 0x100>;
214 reg = <0x0 0x2030000 0x0 0x100>;
788 <0x0 0x31120000 0x0 0x100>,
801 reg = <0x0 0x31150000 0x0 0x100>,
848 reg = <0x0 0x600000 0x0 0x100>;
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_8_0_sh_mask.h127 #define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_WRITE_EN_MASK 0x100
165 #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK 0x100
239 #define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK 0x100
243 #define DC_ABM1_DEBUG_MISC__ABM1_LS_FORCE_INTERRUPT_MASK 0x100
253 #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK 0x100
267 #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK 0x100
399 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN_MASK 0x100
405 #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_DCP_GATE_DISABLE_MASK 0x100
499 #define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT_MASK 0x100
511 #define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x100
[all …]
H A Ddce_11_0_sh_mask.h99 #define DCPG_INTERRUPT_STATUS__DCFE4_POWER_UP_INT_OCCURRED_MASK 0x100
131 #define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_UP_INT_MASK_MASK 0x100
195 #define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_WRITE_EN_MASK 0x100
233 #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK 0x100
307 #define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK 0x100
311 #define DC_ABM1_DEBUG_MISC__ABM1_LS_FORCE_INTERRUPT_MASK 0x100
321 #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK 0x100
335 #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK 0x100
467 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN_MASK 0x100
517 #define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT_MASK 0x100
[all …]
H A Ddce_11_2_sh_mask.h127 #define DCPG_INTERRUPT_STATUS__DCFE4_POWER_UP_INT_OCCURRED_MASK 0x100
163 #define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_UP_INT_MASK_MASK 0x100
235 #define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_WRITE_EN_MASK 0x100
273 #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK 0x100
347 #define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK 0x100
351 #define DC_ABM1_DEBUG_MISC__ABM1_LS_FORCE_INTERRUPT_MASK 0x100
361 #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK 0x100
375 #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK 0x100
507 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN_MASK 0x100
557 #define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT_MASK 0x100
[all …]
H A Ddce_10_0_sh_mask.h127 #define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_WRITE_EN_MASK 0x100
165 #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK 0x100
239 #define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK 0x100
243 #define DC_ABM1_DEBUG_MISC__ABM1_LS_FORCE_INTERRUPT_MASK 0x100
253 #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK 0x100
267 #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK 0x100
399 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN_MASK 0x100
405 #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_DCP_GATE_DISABLE_MASK 0x100
429 #define DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS_MASK 0x100
555 #define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT_MASK 0x100
[all …]
/linux/sound/pci/oxygen/
H A Dwm8776.h43 #define WM8776_UPDATE 0x100
47 /*#define WM8776_UPDATE 0x100*/
107 #define WM8776_ADCHPD 0x100
124 #define WM8776_ADCMS 0x100
135 #define WM8776_ZCA 0x100
143 #define WM8776_LCSEL_ALC_LEFT 0x100
149 #define WM8776_LCEN 0x100
167 #define WM8776_LRBOTH 0x100
/linux/arch/arm64/boot/dts/altera/
H A Dsocfpga_stratix10.dtsi229 reg = <0xffc03200 0x100>;
249 reg = <0xffc03300 0x100>;
269 reg = <0xffc02800 0x100>;
280 reg = <0xffc02900 0x100>;
291 reg = <0xffc02a00 0x100>;
302 reg = <0xffc02b00 0x100>;
313 reg = <0xffc02c00 0x100>;
461 reg = <0xffc03000 0x100>;
469 reg = <0xffc03100 0x100>;
477 reg = <0xffd00000 0x100>;
[all …]
/linux/drivers/net/ethernet/intel/igb/
H A Digb_ethtool.c1011 * spaced 0x100 bytes apart, or in contiguous tables. We assume
1029 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1030 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1031 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1032 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1033 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1034 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1036 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1037 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1038 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
[all …]
/linux/include/linux/mfd/syscon/
H A Datmel-matrix.h14 #define AT91SAM9260_MATRIX_MRCR 0x100
26 #define AT91SAM9263_MATRIX_MRCR 0x100
34 #define AT91SAM9RL_MATRIX_MRCR 0x100
41 #define AT91SAM9G45_MATRIX_MRCR 0x100
49 #define AT91SAM9N12_MATRIX_MRCR 0x100
55 #define AT91SAM9X5_MATRIX_MRCR 0x100
61 #define SAMA5D3_MATRIX_MRCR 0x100
/linux/arch/powerpc/kernel/
H A Dexceptions-64s.S861 * address 0x100 when we are running a relocatable kernel.
948 /* No virt vectors corresponding with 0x0..0x100 */
949 EXC_VIRT_NONE(0x4000, 0x100)
953 * Interrupt 0x100 - System Reset Interrupt (SRESET aka NMI).
978 * send the sreset to 0x100 in the guest if it is not fwnmi capable.
986 IVEC=0x100
993 EXC_REAL_BEGIN(system_reset, 0x100, 0x100)
1038 EXC_REAL_END(system_reset, 0x100, 0x100)
1039 EXC_VIRT_NONE(0x4100, 0x100)
1159 EXC_REAL_BEGIN(machine_check, 0x200, 0x100)
[all …]
/linux/drivers/of/unittest-data/
H A Dtests-address.dtsi76 reg = <0x100000 0x11000 0x100>,
77 <0x100000 0x12000 0x100>,
78 <0x200000 0x11000 0x100>,
79 <0x200000 0x21000 0x100>;
101 reg = <0xf1001000 0x100>,
102 <0xf2002000 0x100>,
103 <0xf3001000 0x100>,
104 <0xf3801000 0x100>,
105 <0xf4001000 0x100>;
/linux/drivers/media/pci/cx25821/
H A Dcx25821-medusa-video.c154 DENC_A_REG_1 + (0x100 * i), &tmp); in medusa_initialize_ntsc()
158 DENC_A_REG_1 + (0x100 * i), value); in medusa_initialize_ntsc()
162 DENC_A_REG_2 + (0x100 * i), &tmp); in medusa_initialize_ntsc()
166 DENC_A_REG_2 + (0x100 * i), value); in medusa_initialize_ntsc()
169 DENC_A_REG_3 + (0x100 * i), &tmp); in medusa_initialize_ntsc()
173 DENC_A_REG_3 + (0x100 * i), value); in medusa_initialize_ntsc()
177 DENC_A_REG_4 + (0x100 * i), &tmp); in medusa_initialize_ntsc()
181 DENC_A_REG_4 + (0x100 * i), value); in medusa_initialize_ntsc()
184 DENC_A_REG_5 + (0x100 * i), &tmp); in medusa_initialize_ntsc()
188 DENC_A_REG_5 + (0x100 * i), value); in medusa_initialize_ntsc()
[all …]
/linux/arch/arm/boot/dts/synaptics/
H A Dberlin2cd.dtsi83 reg = <0xad0000 0x100>;
250 reg = <0x1400 0x100>;
260 reg = <0x1800 0x100>;
270 reg = <0x1c00 0x100>;
278 reg = <0x2000 0x100>;
286 reg = <0x2400 0x100>;
294 reg = <0x2800 0x100>;
445 reg = <0x1000 0x100>;
452 reg = <0x2000 0x100>;
460 reg = <0x3000 0x100>;
[all …]

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