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/freebsd/sys/contrib/device-tree/Bindings/mmc/
H A Dmmc-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MMC Controller Commo
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H A Dfsl-imx-esdhc.txt1 * Freescale Enhanced Secure Digital Host Controller (eSDHC) for i.MX
3 The Enhanced Secure Digital Host Controller on Freescale i.MX family
7 by mmc.txt and the properties used by the sdhci-esdhc-imx driver.
10 - compatible : Should be "fsl,<chip>-esdhc", the supported chips include
11 "fsl,imx25-esdhc"
12 "fsl,imx35-esdhc"
13 "fsl,imx51-esdhc"
14 "fsl,imx53-esdhc"
15 "fsl,imx6q-usdhc"
16 "fsl,imx6sl-usdhc"
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H A Dsamsung,s3cmci.txt1 * Samsung's S3C24XX MMC/SD/SDIO controller device tree bindings
3 Samsung's S3C24XX MMC/SD/SDIO controller is used as a connectivity interface
7 mmc.txt and the properties used by the Samsung S3C24XX MMC/SD/SDIO controller
11 - compatible: should be one of the following
12 - "samsung,s3c2410-sdi": for controllers compatible with s3c2410
13 - "samsung,s3c2412-sdi": for controllers compatible with s3c2412
14 - "samsung,s3c2440-sdi": for controllers compatible with s3c2440
15 - reg: register location and length
16 - interrupts: mmc controller interrupt
17 - clocks: Should reference the controller clock
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H A Dfsl-esdhc.txt1 * Freescale Enhanced Secure Digital Host Controller (eSDHC)
3 The Enhanced Secure Digital Host Controller provides an interface
7 by mmc.txt and the properties used by the sdhci-esdhc driver.
10 - compatible : should be "fsl,esdhc", or "fsl,<chip>-esdhc".
12 "fsl,mpc8536-esdhc"
13 "fsl,mpc8378-esdhc"
14 "fsl,p2020-esdhc"
15 "fsl,p4080-esdhc"
16 "fsl,t1040-esdhc"
17 "fsl,t4240-esdhc"
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H A Dfsl-imx-esdhc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/fsl-imx-esdhc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale Enhanced Secure Digital Host Controller (eSDHC) for i.MX
10 - Shawn Guo <shawnguo@kernel.org>
13 - $ref: sdhci-common.yaml#
16 The Enhanced Secure Digital Host Controller on Freescale i.MX family
20 by mmc.txt and the properties used by the sdhci-esdhc-imx driver.
25 - enum:
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H A Dfsl,esdhc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale Enhanced Secure Digital Host Controller (eSDHC)
10 The Enhanced Secure Digital Host Controller provides an interface
14 - Frank Li <Frank.Li@nxp.com>
19 - enum:
20 - fsl,mpc8536-esdhc
21 - fsl,mpc8378-esdhc
22 - fsl,p2020-esdhc
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H A Dk3-dw-mshc.txt2 Storage Host Controller
4 Read synopsys-dw-mshc.txt for more details
6 The Synopsys designware mobile storage host controller is used to interface
8 differences between the core Synopsys dw mshc controller properties described
9 by synopsys-dw-mshc.txt and the properties used by the Hisilicon specific
10 extensions to the Synopsys Designware Mobile Storage Host Controller.
15 - "hisilicon,hi3660-dw-mshc": for controllers with hi3660 specific extensions.
16 - "hisilicon,hi3670-dw-mshc", "hisilicon,hi3660-dw-mshc": for controllers
18 - "hisilicon,hi4511-dw-mshc": for controllers with hi4511 specific extensions.
19 - "hisilicon,hi6220-dw-mshc": for controllers with hi6220 specific extensions.
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H A Dimg-dw-mshc.txt2 Host Controller
4 The Synopsys designware mobile storage host controller is used to interface
6 differences between the core Synopsys dw mshc controller properties described
7 by synopsys-dw-mshc.txt and the properties used by the Imagination specific
8 extensions to the Synopsys Designware Mobile Storage Host Controller.
13 - "img,pistachio-dw-mshc": for Pistachio SoCs
18 compatible = "img,pistachio-dw-mshc";
23 clock-names = "biu", "ciu";
25 fifo-depth = <0x20>;
26 bus-width = <4>;
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H A Dsunplus,mmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Sunplus MMC Controller
11 - Tony Huang <tonyhuang.sunplus@gmail.com>
12 - Li-hao Kuo <lhjeff911@gmail.com>
15 - $ref: mmc-controller.yaml
20 - sunplus,sp7021-mmc
35 - compatible
36 - reg
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H A Datmel-hsmci.txt3 This controller on atmel products provides an interface for MMC, SD and SDIO
7 by mmc.txt and the properties used by the atmel-mci driver.
12 - compatible: should be "atmel,hsmci"
13 - #address-cells: should be one. The cell is the slot id.
14 - #size-cells: should be zero.
15 - at least one slot node
16 - clock-names: tuple listing input clock names.
18 - clocks: phandles to input clocks.
28 #address-cells = <1>;
29 #size-cells = <0>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/mtd/
H A Dbrcm,brcmnand.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom STB NAND Controller
10 - Brian Norris <computersforpeace@gmail.com>
11 - Kamal Dasu <kdasu.kdev@gmail.com>
12 - William Zhang <william.zhang@broadcom.com>
15 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
16 flash chips. It has a memory-mapped register interface for both control
17 registers and for its data input/output buffer. On some SoCs, this controller
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H A Dnvidia-tegra20-nand.txt1 NVIDIA Tegra NAND Flash controller
4 - compatible: Must be one of:
5 - "nvidia,tegra20-nand"
6 - reg: MMIO address range
7 - interrupts: interrupt output of the NFC controller
8 - clocks: Must contain an entry for each entry in clock-names.
9 See ../clocks/clock-bindings.txt for details.
10 - clock-names: Must include the following entries:
11 - nand
12 - resets: Must contain an entry for each entry in reset-names.
[all …]
H A Dbrcm,brcmnand.txt1 * Broadcom STB NAND Controller
3 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
4 flash chips. It has a memory-mapped register interface for both control
5 registers and for its data input/output buffer. On some SoCs, this controller is
9 This controller was originally designed for STB SoCs (BCM7xxx) but is now
15 - compatible : May contain an SoC-specific compatibility string (see below)
16 to account for any SoC-specific hardware bits that may be
17 added on top of the base core controller.
19 the core NAND controller, of the following form:
21 string, like "brcm,brcmnand-v7.0"
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/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dmarvell,dove-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,dove-pinctrl"
8 - clocks: (optional) phandle of pdma clock
9 - reg: register specifiers of MPP, MPP4, and PMU MPP registers
19 mpp1 1 gpio, pmu, uart2(cts), sdio0(wp), lcd1(pwm), pmu*
23 uart1(cts), lcd-spi(cs1), pmu*
25 mpp5 5 gpio, pmu, uart3(cts), sdio1(wp), spi1(cs), pmu*
31 mpp11 11 gpio, pmu, sata(prsnt), sata-1(act), sdio0(ledctrl),
35 mpp13 13 gpio, pmu, uart2(cts), audio1(extclk), sdio1(wp),
39 mpp16 16 gpio, uart3(rts), sdio0(cd), ac97(sdi1), lcd-spi(cs1)
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx6qdl-rex.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
13 stdout-path = &uart1;
16 reg_3p3v: regulator-3p3v {
17 compatible = "regulator-fixed";
18 regulator-nam
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H A Dimx50-kobo-aura.dts1 // SPDX-License-Identifier: GPL-2.0+
4 // The Kobo Aura e-book reader, model N514. The mainboard is marked as E606F0B.
6 /dts-v1/;
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
16 stdout-pat
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H A Dmba6ulx.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
3 * Copyright 2018-2022 TQ-Systems GmbH
4 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
8 model = "TQ-Systems MBA6ULx Baseboard";
18 stdout-path = &uart1;
22 compatible = "pwm-backlight";
23 power-supply = <&reg_mba6ul_3v3>;
24 enable-gpios = <&expander_out0 4 GPIO_ACTIVE_HIGH>;
29 compatible = "gpio-beeper";
33 gpio_buttons: gpio-keys {
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H A Dimx6sx-sabreauto.dts1 // SPDX-License-Identifier: GPL-2.0
5 /dts-v1/;
11 compatible = "fsl,imx6sx-sabreauto", "fsl,imx6sx";
19 compatible = "gpio-leds";
20 pinctrl-names = "default";
21 pinctrl-0 = <&pinctrl_led>;
23 led-user {
26 linux,default-trigger = "heartbeat";
30 vcc_sd3: regulator-vcc-sd3 {
31 compatible = "regulator-fixed";
[all …]
/freebsd/sys/dev/sdhci/
H A Dsdhci_fdt.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
32 device_t dev; /* Controller device */
40 int num_slots; /* Number of slots on this controller*/
44 bool wp_inverted; /* WP pin is inverted */
45 bool wp_disabled; /* WP pin is not supported */
/freebsd/sys/contrib/device-tree/src/arm/marvell/
H A Dkirkwood-pogoplug-series-4.dts1 // SPDX-License-Identifier: GPL-2.0
3 * kirkwood-pogoplug-series-4.dts - Device tree file for PogoPlug Series 4
10 /dts-v1/;
13 #include "kirkwood-6192.dtsi"
14 #include <dt-bindings/input/linux-event-codes.h>
18 compatible = "cloudengines,pogoplugv4", "marvell,kirkwood-88f6192",
27 stdout-path = "uart0:115200n8";
31 compatible = "gpio-keys";
32 pinctrl-0 = <&pmx_button_eject>;
33 pinctrl-names = "default";
[all …]
/freebsd/sys/contrib/device-tree/src/riscv/allwinner/
H A Dsun20i-d1-nezha.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 // Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
7 * The Nezha-D1 has a 40-pin IO header. Some of these pins are routed
8 * directly to pads on the SoC, others come from an 8-bit pcf857x IO
10 * one set for the pcf857x, and one set for the pio controller.
12 * Lines which are routed to the 40-pin header are named as follows:
15 * <pin#> is the actual pin number of the 40-pi
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/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dac14xx.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
14 #address-cells = <1>;
15 #size-cells = <1>;
26 timebase-frequency = <40000000>; /* 40 MHz (csb/4) */
27 bus-frequency = <160000000>; /* 160 MHz csb bus */
28 clock-frequency = <400000000>; /* 400 MHz ppc core */
49 compatible = "cfi-flash";
51 #address-cells = <1>;
52 #size-cells = <1>;
53 bank-width = <2>;
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/freebsd/sys/arm/ti/
H A Dti_sdhci.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
90 * Note that vendor Beaglebone dtsi files use "ti,omap3-hsmmc" for the am335x.
93 {"ti,am335-sdhci", 1},
94 {"ti,omap3-hsmmc", 1},
95 {"ti,omap4-hsmmc", 1},
105 * access, and the various per-SoC offsets. The SDHCI_REG_OFFSET is how far
127 /* Forward declarations, CAM-relataed */
136 return (bus_read_4(sc->mem_res, off + sc->mmchs_reg_off)); in ti_mmchs_read_4()
143 bus_write_4(sc->mem_res, off + sc->mmchs_reg_off, val); in ti_mmchs_write_4()
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/freebsd/sys/contrib/device-tree/Bindings/iio/chemical/
H A Dsciosense,ens160.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ScioSense ENS160 multi-gas sensor
10 - Gustavo Silva <gustavograzs@gmail.com>
13 Digital Multi-Gas Sensor for Monitoring Indoor Air Quality.
16 https://www.sciosense.com/wp-content/uploads/2023/12/ENS160-Datasheet.pdf
21 - sciosense,ens160
29 vdd-supply: true
30 vddio-supply: true
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/freebsd/sys/contrib/device-tree/src/arm64/amlogic/
H A Dmeson-khadas-vim3.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/leds/common.h>
10 #include <dt-bindings/gpio/meson-g12a-gpio.h>
11 #include <dt-bindings/sound/meson-g12a-tohdmitx.h>
22 stdout-path = "serial0:115200n8";
30 adc-keys {
31 compatible = "adc-keys";
32 io-channels = <&saradc 2>;
33 io-channel-names = "buttons";
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