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/linux/block/
H A Dioprio.c65 SYSCALL_DEFINE3(ioprio_set, int, which, int, who, int, ioprio) in SYSCALL_DEFINE3() argument
81 if (!who) in SYSCALL_DEFINE3()
84 p = find_task_by_vpid(who); in SYSCALL_DEFINE3()
89 if (!who) in SYSCALL_DEFINE3()
92 pgrp = find_vpid(who); in SYSCALL_DEFINE3()
106 uid = make_kuid(current_user_ns(), who); in SYSCALL_DEFINE3()
109 if (!who) in SYSCALL_DEFINE3()
126 if (who) in SYSCALL_DEFINE3()
180 SYSCALL_DEFINE2(ioprio_get, int, which, int, who) in SYSCALL_DEFINE2() argument
192 if (!who) in SYSCALL_DEFINE2()
[all …]
/linux/Documentation/process/
H A D3.Early-stage.rst63 - Who are the users affected by this problem? Which use cases should the
125 Who do you talk to?
139 MAINTAINERS file may, in fact, not be the person who is actually acting in
140 that role currently. So, when there is doubt about who to contact, a
141 useful trick is to use git (and "git log" in particular) to see who is
142 currently active within the subsystem of interest. Look at who is writing
143 patches, and who, if anybody, is attaching Signed-off-by lines to those
144 patches. Those are the people who will be best placed to help with a new
156 command line, it will list the maintainers who should probably receive
161 developers who have no real interest in the code you are modifying.
H A Dmanagement-style.rst7 on who you ask) management style for the linux kernel. It's meant to
18 lead persons, not the people who do traditional management inside
111 This preemptive admission of incompetence might also make the people who
176 trust somebody who is so clearly hiding their true character.
196 Suck up to them, because they are the people who will make your job
225 person who lost their whole 36GB porn-collection because of your
229 Then make the developer who really screwed up (if you can find them) know
232 importantly, they're also likely the person who can fix it. Because, let's
237 glory, because you're the one who gets to say "I screwed up". And if
265 without making it painful to the recipient, who just thinks you're being
H A Dembargoed-hardware-issues.rst35 is a private list of security officers who will help you coordinate a fix
47 vendor, we welcome contact from researchers or individuals who have
98 The hardware security team identifies the developers (domain experts) who
140 developers (domain experts) who should be informed initially about the
154 entities who have already been, or should be, informed about the issue.
160 - The disclosed entities can be contacted to name experts who should
163 - If an expert who is required to handle an issue is employed by a listed
226 to any individual who is not a member of the response team nor to any other
284 organizations, who can answer questions about or provide guidance on the
342 Disclosed parties who want to participate in the communication send a list
H A D6.Followthrough.rst40 people remember who wrote kernel code, but there is little lasting fame
41 for those who reviewed it. So reviewers can get grumpy, especially when
152 may be a new round of comments from developers who had not been aware of
155 though; you still need to be responsive to developers who have questions or
186 development community remembers developers who lose interest in their code
H A Dconclave.rst11 others who can do that work when the need arises.
23 as possible in a way that maximizes the number of people who can
/linux/fs/
H A Dsuper.c43 static int thaw_super_locked(struct super_block *sb, enum freeze_holder who,
1903 static inline int freeze_inc(struct super_block *sb, enum freeze_holder who) in freeze_inc() argument
1905 WARN_ON_ONCE((who & ~FREEZE_FLAGS)); in freeze_inc()
1906 WARN_ON_ONCE(hweight32(who & FREEZE_HOLDERS) > 1); in freeze_inc()
1908 if (who & FREEZE_HOLDER_KERNEL) in freeze_inc()
1910 if (who & FREEZE_HOLDER_USERSPACE) in freeze_inc()
1915 static inline int freeze_dec(struct super_block *sb, enum freeze_holder who) in freeze_dec() argument
1917 WARN_ON_ONCE((who & ~FREEZE_FLAGS)); in freeze_dec()
1918 WARN_ON_ONCE(hweight32(who & FREEZE_HOLDERS) > 1); in freeze_dec()
1920 if ((who & FREEZE_HOLDER_KERNEL) && sb->s_writers.freeze_kcount) in freeze_dec()
[all …]
/linux/arch/s390/kvm/
H A Dtrace-s390.h126 TP_PROTO(__u64 type, __u32 parm, __u64 parm64, int who),
127 TP_ARGS(type, parm, parm64, who),
133 __field(int, who)
140 __entry->who = who;
144 (__entry->who == 1) ? " (from kernel)" :
145 (__entry->who == 2) ? " (from user)" : "",
/linux/Documentation/filesystems/nfs/
H A Dnfsd-maintainer-entry-profile.rst495 - **Contributor** : Anyone who submits a code change, bug fix,
499 - **Outside Contributor** : A contributor who is not a regular actor
500 in the Linux NFS community. This can mean someone who contributes
501 to other parts of the kernel, or someone who just noticed a
504 - **Reviewer** : Someone who is named in the MAINTAINERS file as a
505 reviewer is an area expert who can request changes to contributed
508 - **External Reviewer** : Someone who is not named in the
509 MAINTAINERS file as a reviewer, but who is an area expert.
511 security, or persistent storage expertise, or developers who
524 - **Bug Triager** : Someone who is a first responder to bug reports
/linux/Documentation/block/
H A Dioprio.rst86 static inline int ioprio_set(int which, int who, int ioprio)
88 return syscall(__NR_ioprio_set, which, who, ioprio);
91 static inline int ioprio_get(int which, int who)
93 return syscall(__NR_ioprio_get, which, who);
/linux/Documentation/scsi/
H A DFlashPoint.rst93 caused grief for many people who inadvertently purchased a system expecting
100 made available, and that Linux users who mistakenly ordered systems with
104 assist the people who initially purchased a FlashPoint for a supported
105 operating system and then later decided to run Linux, or those who had
125 are people at BusLogic who would rather not release the details of the
/linux/kernel/
H A Dsys.c259 SYSCALL_DEFINE3(setpriority, int, which, int, who, int, niceval) in SYSCALL_DEFINE3() argument
281 if (who) in SYSCALL_DEFINE3()
282 p = find_task_by_vpid(who); in SYSCALL_DEFINE3()
289 if (who) in SYSCALL_DEFINE3()
290 pgrp = find_vpid(who); in SYSCALL_DEFINE3()
300 uid = make_kuid(cred->user_ns, who); in SYSCALL_DEFINE3()
302 if (!who) in SYSCALL_DEFINE3()
329 SYSCALL_DEFINE2(getpriority, int, which, int, who) in SYSCALL_DEFINE2() argument
344 if (who) in SYSCALL_DEFINE2()
345 p = find_task_by_vpid(who); in SYSCALL_DEFINE2()
[all …]
/linux/tools/perf/pmu-events/arch/x86/rocketlake/
H A Dfrontend.json41 "BriefDescription": "Retired Instructions who experienced DSB miss.",
52 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
63 "BriefDescription": "Retired Instructions who experienced iTLB true miss.",
74 "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
80 "PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss.",
85 "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.",
91 "PublicDescription": "Counts retired Instructions who experienced Instruction L2 Cache true miss.",
217 "BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.",
/linux/tools/perf/pmu-events/arch/x86/icelakex/
H A Dfrontend.json41 "BriefDescription": "Retired Instructions who experienced DSB miss.",
52 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
63 "BriefDescription": "Retired Instructions who experienced iTLB true miss.",
74 "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
80 "PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss.",
85 "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.",
91 "PublicDescription": "Counts retired Instructions who experienced Instruction L2 Cache true miss.",
217 "BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.",
/linux/tools/perf/pmu-events/arch/x86/tigerlake/
H A Dfrontend.json41 "BriefDescription": "Retired Instructions who experienced DSB miss.",
52 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
63 "BriefDescription": "Retired Instructions who experienced iTLB true miss.",
74 "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
80 "PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss.",
85 "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.",
91 "PublicDescription": "Counts retired Instructions who experienced Instruction L2 Cache true miss.",
217 "BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.",
/linux/tools/perf/pmu-events/arch/x86/icelake/
H A Dfrontend.json41 "BriefDescription": "Retired Instructions who experienced DSB miss.",
52 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
63 "BriefDescription": "Retired Instructions who experienced iTLB true miss.",
74 "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
80 "PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss.",
85 "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.",
91 "PublicDescription": "Counts retired Instructions who experienced Instruction L2 Cache true miss.",
217 "BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.",
/linux/tools/perf/pmu-events/arch/x86/graniterapids/
H A Dfrontend.json49 "BriefDescription": "Retired Instructions who experienced DSB miss.",
63 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
74 "BriefDescription": "Retired Instructions who experienced iTLB true miss.",
88 "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
94 "PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss. Available PDIST counters: 0",
102 "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.",
108 "PublicDescription": "Counts retired Instructions who experienced Instruction L2 Cache true miss. Available PDIST counters: 0",
273 "BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.",
437 "PublicDescription": "This event counts a subset of the Topdown Slots event that when no operation was delivered to the back-end pipeline due to instruction fetch limitations when the back-end could have accepted more operations. Common examples include instruction cache misses or x86 instruction decode limitations. The count may be distributed among unhalted logical processors (hyper-threads) who share the same physical core, in processors that support Intel Hyper-Threading Technology. Software can use this event as the numerator for the Frontend Bound metric (or top-level category) of the Top-down Microarchitecture Analysis method.",
/linux/tools/perf/pmu-events/arch/x86/emeraldrapids/
H A Dfrontend.json38 "BriefDescription": "Retired Instructions who experienced DSB miss.",
49 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
60 "BriefDescription": "Retired Instructions who experienced iTLB true miss.",
71 "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
77 "PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss. Available PDIST counters: 0",
82 "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.",
88 "PublicDescription": "Counts retired Instructions who experienced Instruction L2 Cache true miss. Available PDIST counters: 0",
225 "BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.",
/linux/tools/perf/pmu-events/arch/x86/sapphirerapids/
H A Dfrontend.json38 "BriefDescription": "Retired Instructions who experienced DSB miss.",
49 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
60 "BriefDescription": "Retired Instructions who experienced iTLB true miss.",
71 "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
77 "PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss. Available PDIST counters: 0",
82 "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.",
88 "PublicDescription": "Counts retired Instructions who experienced Instruction L2 Cache true miss. Available PDIST counters: 0",
225 "BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.",
/linux/tools/perf/pmu-events/arch/x86/meteorlake/
H A Dfrontend.json72 "BriefDescription": "Retired Instructions who experienced DSB miss.",
121 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
151 "BriefDescription": "Retired Instructions who experienced iTLB true miss.",
163 "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
169 "PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss. Available PDIST counters: 0",
175 "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.",
181 "PublicDescription": "Counts retired Instructions who experienced Instruction L2 Cache true miss. Available PDIST counters: 0",
361 "BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.",
553 "PublicDescription": "This event counts a subset of the Topdown Slots event that when no operation was delivered to the back-end pipeline due to instruction fetch limitations when the back-end could have accepted more operations. Common examples include instruction cache misses or x86 instruction decode limitations. The count may be distributed among unhalted logical processors (hyper-threads) who share the same physical core, in processors that support Intel Hyper-Threading Technology. Software can use this event as the numerator for the Frontend Bound metric (or top-level category) of the Top-down Microarchitecture Analysis method.",
/linux/tools/perf/pmu-events/arch/x86/alderlake/
H A Dfrontend.json52 "BriefDescription": "Retired Instructions who experienced DSB miss.",
64 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
76 "BriefDescription": "Retired Instructions who experienced iTLB true miss.",
88 "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
94 "PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss. Available PDIST counters: 0",
100 "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.",
106 "PublicDescription": "Counts retired Instructions who experienced Instruction L2 Cache true miss. Available PDIST counters: 0",
256 "BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.",
/linux/tools/perf/pmu-events/arch/x86/pantherlake/
H A Dother.json3 "BriefDescription": "Count all other hardware assists or traps that are not necessarily architecturally exposed (through a software handler) beyond FP; SSE-AVX mix and A/D assists who are counted by dedicated sub-events.",
7 "PublicDescription": "Count all other hardware assists or traps that are not necessarily architecturally exposed (through a software handler) beyond FP; SSE-AVX mix and A/D assists who are counted by dedicated sub-events. This includes, but not limited to, assists at EXE or MEM uop writeback like AVX* load/store/gather/scatter (non-FP GSSE-assist ) , assists generated by ROB like PEBS and RTIT, Uncore trap, RAR (Remote Action Request) and CET (Control flow Enforcement Technology) assists.",
H A Dfrontend.json100 "BriefDescription": "Retired Instructions who experienced DSB miss.",
112 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
134 "BriefDescription": "Retired Instructions who experienced iTLB true miss.",
146 "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
152 "PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss. Available PDIST counters: 0,1",
158 "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.",
164 "PublicDescription": "Counts retired Instructions who experienced Instruction L2 Cache true miss. Available PDIST counters: 0,1",
314 "BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.",
/linux/Documentation/mm/
H A Dpage_owner.rst2 page owner: Tracking about who allocated each page
8 page owner is for the tracking about who allocated each page.
16 using it for analyzing who allocate each page is rather complex. We need
171 See the result about who allocated each page
/linux/Documentation/virt/kvm/s390/
H A Ds390-pv-dump.rst16 confidentiality until the dump is in the hands of the VM owner who
19 The confidentiality of the VM dump is ensured by the Ultravisor who

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