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/linux/drivers/staging/greybus/
H A Dgpio.c62 static int gb_gpio_activate_operation(struct gb_gpio_controller *ggc, u8 which) in gb_gpio_activate_operation() argument
72 request.which = which; in gb_gpio_activate_operation()
80 ggc->lines[which].active = true; in gb_gpio_activate_operation()
86 u8 which) in gb_gpio_deactivate_operation() argument
93 request.which = which; in gb_gpio_deactivate_operation()
97 dev_err(dev, "failed to deactivate gpio %u\n", which); in gb_gpio_deactivate_operation()
101 ggc->lines[which].active = false; in gb_gpio_deactivate_operation()
108 u8 which) in gb_gpio_get_direction_operation() argument
116 request.which = which; in gb_gpio_get_direction_operation()
126 which, direction); in gb_gpio_get_direction_operation()
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H A Dpwm.c44 static int gb_pwm_activate_operation(struct pwm_chip *chip, u8 which) in gb_pwm_activate_operation() argument
51 request.which = which; in gb_pwm_activate_operation()
66 static int gb_pwm_deactivate_operation(struct pwm_chip *chip, u8 which) in gb_pwm_deactivate_operation() argument
73 request.which = which; in gb_pwm_deactivate_operation()
89 u8 which, u32 duty, u32 period) in gb_pwm_config_operation() argument
96 request.which = which; in gb_pwm_config_operation()
114 u8 which, u8 polarity) in gb_pwm_set_polarity_operation() argument
121 request.which = which; in gb_pwm_set_polarity_operation()
137 static int gb_pwm_enable_operation(struct pwm_chip *chip, u8 which) in gb_pwm_enable_operation() argument
144 request.which = which; in gb_pwm_enable_operation()
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/linux/tools/perf/pmu-events/arch/powerpc/power10/
H A Dpipeline.json5 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline suffered a TLB miss or…
10 …"BriefDescription": "Cycles in which the next-to-complete (NTC) instruction is held at dispatch fo…
35 "BriefDescription": "Cycles in which an instruction reload is pending to satisfy a demand miss."
55 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load…
60 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline finished at dispatch a…
75 …"BriefDescription": "Cycles in which the next-to-complete (NTC) instruction is held at dispatch be…
80 …"BriefDescription": "Cycles in which the next-to-complete (NTC) instruction is held at dispatch be…
85 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load…
90 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was executing in the s…
95 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was a lwsync waiting t…
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/linux/tools/testing/selftests/powerpc/dexcr/
H A Ddexcr_test.c16 static int dexcr_prctl_onexec_test_child(unsigned long which, const char *status) in dexcr_prctl_onexec_test_child() argument
19 unsigned long aspect = pr_which_to_aspect(which); in dexcr_prctl_onexec_test_child()
20 int ctrl = pr_get_dexcr(which); in dexcr_prctl_onexec_test_child()
48 static int dexcr_prctl_aspect_test(unsigned long which) in dexcr_prctl_aspect_test() argument
50 unsigned long aspect = pr_which_to_aspect(which); in dexcr_prctl_aspect_test()
57 SKIP_IF_MSG(!pr_dexcr_aspect_supported(which), "DEXCR aspect not supported"); in dexcr_prctl_aspect_test()
58 SKIP_IF_MSG(!pr_dexcr_aspect_editable(which), "DEXCR aspect not editable with prctl"); in dexcr_prctl_aspect_test()
61 err = pr_set_dexcr(which, PR_PPC_DEXCR_CTRL_SET | PR_PPC_DEXCR_CTRL_CLEAR); in dexcr_prctl_aspect_test()
66 err = pr_set_dexcr(which, PR_PPC_DEXCR_CTRL_SET_ONEXEC | PR_PPC_DEXCR_CTRL_CLEAR_ONEXEC); in dexcr_prctl_aspect_test()
72 err = pr_set_dexcr(which, PR_PPC_DEXCR_CTRL_SET); in dexcr_prctl_aspect_test()
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/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a76/
H A Dcache.json3 "PublicDescription": "This event counts any instruction fetch which misses in the cache.",
11 …re operation or page table walk access which causes data to be read from outside the L1, including…
15 …store operation or page table walk access which looks up in the L1 data cache. In particular, any …
23 …or Level 0 Macro-op cache access. This event counts any instruction fetch which accesses the L1 in…
31 …"PublicDescription": "This event counts any transaction from L1 which looks up in the L2 cache, an…
35 …L2 data cache refill. This event counts any cacheable transaction from L1 which causes data to be …
39 …which return data, regardless of whether they cause an invalidation. Invalidations from the L2 whi…
43 …line write into the L2 cache which does not cause a linefill, including write-backs from L1 to L2 …
47 …"PublicDescription": "This event counts any load or store operation which accesses the data L1 TLB…
52 …"PublicDescription": "This event counts any instruction fetch which accesses the instruction L1 TL…
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/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/
H A Dbranch.json18 … "Predicted conditional branch executed.This event counts when any branch which can be predicted b…
21 … "Predicted conditional branch executed.This event counts when any branch which can be predicted b…
24 …"Indirect branch mis-predicted.This event counts when any indirect branch which can be predicted b…
27 …"Indirect branch mis-predicted.This event counts when any indirect branch which can be predicted b…
30 …ted due to address mis-compare.This event counts when any indirect branch which can be predicted b…
33 …ted due to address mis-compare.This event counts when any indirect branch which can be predicted b…
36 …which can be predicted by the conditional predictor is retired, and has mis-predicted the conditio…
39 …which can be predicted by the conditional predictor is retired, and has mis-predicted the conditio…
42 …ith predicted address executed.This event counts when any indirect branch which can be predicted b…
45 …ith predicted address executed.This event counts when any indirect branch which can be predicted b…
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/linux/tools/testing/kunit/test_data/
H A Dtest_is_test_passed-no_tests_run_no_header.log39 Using a channel type which is configured out of UML
41 Using a channel type which is configured out of UML
43 Using a channel type which is configured out of UML
45 Using a channel type which is configured out of UML
47 Using a channel type which is configured out of UML
49 Using a channel type which is configured out of UML
51 Using a channel type which is configured out of UML
53 Using a channel type which is configured out of UML
55 Using a channel type which is configured out of UML
57 Using a channel type which is configured out of UML
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H A Dtest_output_isolated_correctly.log61 Using a channel type which is configured out of UML
63 Using a channel type which is configured out of UML
65 Using a channel type which is configured out of UML
67 Using a channel type which is configured out of UML
69 Using a channel type which is configured out of UML
71 Using a channel type which is configured out of UML
73 Using a channel type which is configured out of UML
75 Using a channel type which is configured out of UML
77 Using a channel type which is configured out of UML
79 Using a channel type which is configured out of UML
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/linux/drivers/mtd/chips/
H A DKconfig22 This option enables JEDEC-style probing of flash chips which are not
24 CFI-targeted flash drivers for any chips which are identified which
40 configuration options which allow you to do so.
49 This option defines the way in which the CPU attempts to arrange
51 'NO', which is the default when CONFIG_MTD_CFI_ADV_OPTIONS isn't
79 some other configuration options which would allow you to reduce
82 which are supported by the current code will be enabled.
88 If you wish to support CFI devices on a physical bus which is
95 If you wish to support CFI devices on a physical bus which is
102 If you wish to support CFI devices on a physical bus which is
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/linux/net/bridge/netfilter/
H A DKconfig110 This option adds the among match, which allows matching the MAC source
119 This option adds the ARP match, which allows ARP and RARP header field
127 This option adds the IP match, which allows basic IP header field
136 This option adds the IP6 match, which allows basic IPV6 header field
144 This option adds the limit match, which allows you to control
145 the rate at which a rule can be matched. This match is the
154 This option adds the mark match, which allows matching frames based on
164 This option adds the packet type match, which allows matching on the
174 This option adds the Spanning Tree Protocol match, which
182 This option adds the 802.1Q vlan match, which allows the filtering of
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/linux/net/netfilter/ipset/
H A DKconfig32 This option adds the bitmap:ip set type support, by which one
41 This option adds the bitmap:ip,mac set type support, by which one
50 This option adds the bitmap:port set type support, by which one
59 This option adds the hash:ip set type support, by which one
69 This option adds the hash:ip,mark set type support, by which one
78 This option adds the hash:ip,port set type support, by which one
87 This option adds the hash:ip,port,ip set type support, by which
97 This option adds the hash:ip,port,net set type support, by which
107 This option adds the hash:ip,mac set type support, by which
116 This option adds the hash:mac set type support, by which
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/linux/include/uapi/linux/
H A Dv4l2-subdev.h32 * @which: format type (from enum v4l2_subdev_format_whence)
39 __u32 which; member
48 * @which: format type (from enum v4l2_subdev_format_whence)
59 __u32 which; member
77 * @which: format type (from enum v4l2_subdev_format_whence)
86 __u32 which; member
101 * @which: format type (from enum v4l2_subdev_format_whence)
113 __u32 which; member
123 * @which: interval type (from enum v4l2_subdev_format_whence)
130 __u32 which; member
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/linux/Documentation/arch/x86/
H A Dmds.rst17 MSBDS leaks Store Buffer Entries which can be speculatively forwarded to a
20 memory address, which can be exploited under certain conditions. Store
23 buffer is repartitioned which can expose data from one thread to the other.
26 L1 miss situations and to hold data which is returned or sent in response
29 deallocated it can retain the stale data of the preceding operations which
30 can then be forwarded to a faulting or assisting load operation, which can
37 contain stale data from a previous operation which can be forwarded to
38 faulting or assisting loads under certain conditions, which again can be
56 - to have a disclosure gadget which exposes the speculatively accessed
59 - to control the pointer through which the disclosure gadget exposes the
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/linux/drivers/md/dm-vdo/
H A Drecovery-journal.h24 * The recovery_journal provides a log of all block mapping and reference count changes which have
40 * The journal also contains a set of in-memory blocks which are used to buffer up entries until
43 * has a vio which is used to commit that block to disk. The vio's data is the on-disk
44 * representation of the journal block. In addition each in-memory block has a buffer which is used
52 * committed, the requesting VIO will be attached to the in-memory block to which the caller's
57 * to the block's vio which is then written, automatically waking all of the waiters when it
58 * completes. When the write completes, any entries which accumulated in the block are copied to
71 * the one it references, in which case it increments the count on the earlier journal block and
94 /* The number of logical zones which may hold locks */
96 /* The number of physical zones which may hold locks */
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H A Daction-manager.h14 * as the block map or slab depot). Each action manager is tied to a specific context for which it
18 * action manager from a single thread (which thread is determined when the action manager is
37 * A function which is to be applied asynchronously to a set of zones.
38 * @context: The object which holds the per-zone context for the action
39 * @zone_number: The number of zone to which the action is being applied
46 * A function which is to be applied asynchronously on an action manager's initiator thread as the
48 * @context: The object which holds the per-zone context for the action
54 * A function which will run on the action manager's initiator thread as the conclusion of an
56 * @context: The object which holds the per-zone context for the action
64 * @context: The object which holds the per-zone context for the action
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/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a73/
H A Dpipeline.json15 "PublicDescription": "Duration for which all slots in the Load-Store Unit are busy",
18 "BriefDescription": "Duration for which all slots in the Load-Store Unit are busy"
21 "PublicDescription": "Duration for which all slots in the load-store issue queue are busy",
24 "BriefDescription": "Duration for which all slots in the load-store issue queue are busy"
27 … "PublicDescription": "Duration for which all slots in the data processing issue queue are busy",
30 … "BriefDescription": "Duration for which all slots in the data processing issue queue are busy"
33 "PublicDescription": "Duration for which all slots in the Data Engine issue queue are busy",
36 "BriefDescription": "Duration for which all slots in the Data Engine issue queue are busy"
/linux/Documentation/timers/
H A Dhighres.rst6 and beyond". The paper is part of the OLS 2006 Proceedings Volume 1, which can
13 The slides contain five figures (pages 2, 15, 18, 20, 22), which illustrate the
37 The main differences to the timer wheel, which holds the armed timer_list type
51 sources, which are registered in the framework and selected on a quality based
53 initializes data structures, which are used by the generic time keeping code to
91 service handler, which is almost inherently hardware dependent.
114 a function pointer in the device description structure, which has to be called
125 The framework adds about 700 lines of code which results in a 2KB increase of
153 which inform hrtimers about availability of new hardware. hrtimers validates
155 switching to high resolution mode. This ensures also that a kernel which is
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/linux/Documentation/security/tpm/
H A Dtpm-security.rst16 PTT, which is a software TPM running inside a software environment
17 close to the CPU, which are subject to different attacks, but right at
19 hardware TPM, which is the use case discussed here.
25 interposer which is a simple external device that can be installed in
46 which would be an annoying denial of service attack. However, there
56 the PCRs and then send down their own measurements which would
64 on some sort of mechanism for protection which would change over TPM
72 interception which HMAC protection alone cannot protect against, so
80 asymmetric secret must be established which must also be unknown to
82 and storage seeds, which can be used to derive asymmetric keys.
[all …]
/linux/arch/riscv/kernel/
H A Dfpu.S108 #define get_f32(which) fmv.x.s a0, which; j 2f argument
109 #define put_f32(which) fmv.s.x which, a1; j 2f argument
111 # define get_f64(which) fmv.x.d a0, which; j 2f argument
112 # define put_f64(which) fmv.d.x which, a1; j 2f argument
114 # define get_f64(which) fsd which, 0(a1); j 2f argument
115 # define put_f64(which) fld which, 0(a1); j 2f argument
217 * a1 = If xlen == 32, pointer which should be loaded with the FP register value
218 * or unused if xlen == 64. In which case the FP register value is returned
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmediatek,mt8365-pinctrl.yaml83 100: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
84 101: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
85 102: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
86 103: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
97 100: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
98 101: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
99 102: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
100 103: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
155 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
156 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
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/linux/Documentation/process/
H A D3.Early-stage.rst32 misuse of the LSM framework (which is not intended to confer privileges
33 onto processes which they would not otherwise have) and a risk to system
61 - What, exactly, is the problem which needs to be solved?
63 - Who are the users affected by this problem? Which use cases should the
78 - It may well be that the problem is addressed by the kernel in ways which
80 features and capabilities which are not immediately obvious. Not all
83 driver which duplicated an existing driver that the new author had been
84 unaware of. Code which reinvents existing wheels is not only wasteful;
87 - There may be elements of the proposed solution which will not be
96 clear lesson: kernel code which is designed and developed behind closed
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/linux/arch/x86/math-emu/
H A DREADME26 which was my 80387 emulator for early versions of djgpp (gcc under
27 msdos); wm-emu387 was in turn based upon emu387 which was written by
61 is not the obvious one which most people seem to use, but is designed
64 seen it. It is based upon one of those ideas which one carries around
74 a value of pi which is accurate to more than 128 bits. As a consequence,
78 80486, which uses a value of pi which is accurate to 66 bits.
87 variables. The code which accesses user memory is confined to five
97 form of re-entrancy which is required by the Linux kernel.
103 are fewer than those which applied to the 1.xx series of the emulator.
139 able to find the instruction which caused the device-not-present
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/linux/include/linux/
H A Ddevm-helpers.h6 * Functions which do automatically cancel operations or release resources upon
10 * management which can be source of annoying, rarely occurring,
22 * and schedule a work item which won't be cancelled because remove() was
36 * @dev: Device which lifetime work is bound to
40 * Initialize delayed work which is automatically cancelled when driver is
41 * detached. A few drivers need delayed work which must be cancelled before
61 * @dev: Device which lifetime work is bound to
65 * Initialize work which is automatically cancelled when driver is detached.
66 * A few drivers need to queue work which must be cancelled before driver
/linux/drivers/memory/samsung/
H A Dexynos5422-dmc.c56 * A value for register DREX_PMNC_PPC which should be written to reset
63 * A value for register DREX_PMNC_PPC which does the reset of all performance
74 /* A value for register DREX_PPCCLKCON which enables performance events clock.
81 * Values which are used to enable counters, interrupts or configure flags of
88 * Performance event types which are used for setting the preferred event
91 * These settings should be written to the configuration register which manages
150 * The main structure for the Dynamic Memory Controller which covers clocks,
283 * @dmc: device for which the information is checked
303 * @dmc: device for which the new settings is going to be applied
306 * Changes the register set, which holds timing parameters.
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/linux/Documentation/admin-guide/hw-vuln/
H A Dl1tf.rst4 L1 Terminal Fault is a hardware vulnerability which allows unprivileged
5 speculative access to data which is available in the Level 1 Data Cache
6 when the page table entry controlling the virtual address, which is used
24 - Intel processors which have the ARCH_CAP_RDCL_NO bit set in the
46 If an instruction accesses a virtual address for which the relevant page
72 PTE which is marked non present. This allows a malicious user space
73 application to attack the physical memory to which these PTEs resolve.
79 inversion, which is permanently enabled and has no performance
80 impact. The kernel ensures that the address bits of PTEs, which are not
90 OSes, which can control the PTEs directly, and malicious guest user
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