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/linux/arch/mips/mm/
H A Dc-octeon.c184 c->icache.ways = 1 + ((config1 >> 16) & 7); in probe_octeon()
187 c->icache.sets * c->icache.ways * c->icache.linesz; in probe_octeon()
188 c->icache.waybit = ffs(icache_size / c->icache.ways) - 1; in probe_octeon()
194 c->dcache.ways = 64; in probe_octeon()
196 c->dcache.sets * c->dcache.ways * c->dcache.linesz; in probe_octeon()
197 c->dcache.waybit = ffs(dcache_size / c->dcache.ways) - 1; in probe_octeon()
204 c->icache.ways = 37; in probe_octeon()
206 icache_size = c->icache.sets * c->icache.ways * c->icache.linesz; in probe_octeon()
209 c->dcache.ways = 32; in probe_octeon()
211 dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz; in probe_octeon()
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H A Dc-r4k.c233 unsigned long ws_end = current_cpu_data.icache.ways << in tx49_blast_icache32()
1010 c->icache.ways = 2; in probe_pcache()
1015 c->dcache.ways = 2; in probe_pcache()
1024 c->icache.ways = 2; in probe_pcache()
1029 c->dcache.ways = 2; in probe_pcache()
1038 c->icache.ways = 4; in probe_pcache()
1043 c->dcache.ways = 4; in probe_pcache()
1059 c->icache.ways = 1; in probe_pcache()
1064 c->dcache.ways = 1; in probe_pcache()
1076 c->icache.ways = 2; in probe_pcache()
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H A Dsc-mips.c170 c->scache.ways = assoc + 1; in mips_sc_probe_cm3()
220 c->scache.ways = tmp + 1; in mips_sc_probe()
227 * According to config2 it would be 5-ways, but that is in mips_sc_probe()
232 c->scache.ways = 4; in mips_sc_probe()
236 * According to config2 it would be 5-ways and 512-sets, in mips_sc_probe()
242 c->scache.ways = 4; in mips_sc_probe()
H A Dsc-rm7k.c238 c->scache.ways = 4; in rm7k_sc_init()
239 c->scache.waybit= __ffs(scache_size / c->scache.ways); in rm7k_sc_init()
240 c->scache.waysize = scache_size / c->scache.ways; in rm7k_sc_init()
241 c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways); in rm7k_sc_init()
268 c->tcache.ways = 1; in rm7k_sc_init()
/linux/arch/sh/kernel/cpu/sh4/
H A Dprobe.c38 boot_cpu_data.icache.ways = 1; in cpu_probe()
47 boot_cpu_data.dcache.ways = 1; in cpu_probe()
67 boot_cpu_data.icache.ways = 4; in cpu_probe()
68 boot_cpu_data.dcache.ways = 4; in cpu_probe()
171 boot_cpu_data.icache.ways = 2; in cpu_probe()
172 boot_cpu_data.dcache.ways = 2; in cpu_probe()
176 boot_cpu_data.icache.ways = 2; in cpu_probe()
177 boot_cpu_data.dcache.ways = 2; in cpu_probe()
192 boot_cpu_data.icache.ways = 2; in cpu_probe()
193 boot_cpu_data.dcache.ways = 2; in cpu_probe()
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/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a73/
H A Dcache.json54 "PublicDescription": "Number of ways read in the instruction cache - Tag RAM",
57 "BriefDescription": "Number of ways read in the instruction cache - Tag RAM"
60 "PublicDescription": "Number of ways read in the instruction cache - Data RAM",
63 "BriefDescription": "Number of ways read in the instruction cache - Data RAM"
66 "PublicDescription": "Number of ways read in the instruction BTAC RAM",
69 "BriefDescription": "Number of ways read in the instruction BTAC RAM"
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm2836.dtsi58 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
61 i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
72 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
75 i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
86 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
89 i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
100 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
103 i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
118 cache-sets = <1024>; // 512KiB(size)/64(line-size)=8192ways/8-way set
H A Dbcm2837.dtsi57 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
60 i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
72 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
75 i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
87 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
90 i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
102 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
105 i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
120 cache-sets = <512>; // 512KiB(size)/64(line-size)=8192ways/16-way set
H A Dbcm2835.dtsi29 d-cache-sets = <256>; // 16KiB(size)/16(line-size)=1024ways/4-way set
32 i-cache-sets = <256>; // 16KiB(size)/16(line-size)=1024ways/4-way set
/linux/arch/sh/mm/
H A Dcache-sh7705.c33 unsigned long ways, waysize, addrstart; in cache_wback_all() local
35 ways = current_cpu_data.dcache.ways; in cache_wback_all()
58 } while (--ways); in cache_wback_all()
82 unsigned long ways, waysize, addrstart; in __flush_dcache_page() local
103 ways = current_cpu_data.dcache.ways; in __flush_dcache_page()
125 } while (--ways); in __flush_dcache_page()
H A Dtlb-sh3.c58 int i, ways = MMU_NTLB_WAYS; in local_flush_tlb_one() local
71 ways = 1; /* we already know the way .. */ in local_flush_tlb_one()
74 for (i = 0; i < ways; i++) in local_flush_tlb_one()
H A Dcache-sh2a.c41 /* Set associative bit to hit all ways */ in sh2a_invalidate_line()
60 nr_ways = current_cpu_data.dcache.ways; in sh2a__flush_wback_region()
107 int nr_ways = current_cpu_data.dcache.ways; in sh2a__flush_purge_region()
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a75/
H A Dcache.json111 "PublicDescription": "Number of ways read in the instruction cache - Tag RAM",
114 "BriefDescription": "Number of ways read in the instruction cache - Tag RAM"
117 "PublicDescription": "Number of ways read in the instruction cache - Data RAM",
120 "BriefDescription": "Number of ways read in the instruction cache - Data RAM"
123 "PublicDescription": "Number of ways read in the instruction BTAC RAM",
126 "BriefDescription": "Number of ways read in the instruction BTAC RAM"
/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Drvu_npc_hash.c474 /* Check all the 4 ways for a free slot. */ in rvu_npc_exact_alloc_mem_table_entry()
476 for (i = 0; i < table->mem_table.ways; i++) { in rvu_npc_exact_alloc_mem_table_entry()
771 * @ways: MEM table ways.
784 static int rvu_npc_exact_add_to_list(struct rvu *rvu, enum npc_exact_opc_type opc_type, u8 ways, in rvu_npc_exact_add_to_list() argument
792 WARN_ON(ways >= NPC_EXACT_TBL_MAX_WAYS); in rvu_npc_exact_add_to_list()
814 lhead = &table->lhead_mem_tbl_entry[ways]; in rvu_npc_exact_add_to_list()
832 entry->ways = ways; in rvu_npc_exact_add_to_list()
868 * @ways: ways for MEM table.
872 static void rvu_npc_exact_mem_table_write(struct rvu *rvu, int blkaddr, u8 ways, in rvu_npc_exact_mem_table_write() argument
875 rvu_write64(rvu, blkaddr, NPC_AF_EXACT_MEM_ENTRY(ways, index), mdata); in rvu_npc_exact_mem_table_write()
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/linux/arch/mips/include/asm/octeon/
H A Dcvmx-l2c.h188 * the cache 'ways' that a core can evict from.
197 * @mask: The partitioning of the ways expressed as a binary
204 * @note If any ways are blocked for all cores and the HW blocks, then
205 * those ways will never have any cache lines evicted from them.
207 * ways regardless of the partitioning.
215 * the cache 'ways' that a core can evict from.
223 * @mask: The partitioning of the ways expressed as a binary
230 * @note If any ways are blocked for all cores and the HW blocks, then
231 * those ways will never have any cache lines evicted from them.
233 * ways regardless of the partitioning.
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/linux/arch/arm64/boot/dts/broadcom/
H A Dbcm2712.dtsi61 d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
64 i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
71 cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set
85 d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
88 i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
95 cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set
109 d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
112 i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
119 cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set
133 d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
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/linux/arch/sh/kernel/cpu/
H A Dinit.c126 unsigned long ways, waysize, addrstart; in cache_init() local
144 ways = 1; in cache_init()
147 ways = current_cpu_data.dcache.ways; in cache_init()
159 } while (--ways); in cache_init()
170 if (current_cpu_data.dcache.ways > 1) in cache_init()
200 CSHAPE((desc).way_size * (desc).ways, ilog2((desc).linesz), (desc).ways)
/linux/arch/arc/mm/
H A Dtlb.c22 unsigned int ver, pg_sz_k, s_pg_sz_m, pae, sets, ways; member
139 int num_tlb = mmu->sets * mmu->ways; in local_flush_tlb_all()
579 mmu->ways = 1 << mmu3->ways; in arc_mmu_mumbojumbo()
588 mmu->ways = mmu4->n_ways * 2; in arc_mmu_mumbojumbo()
603 mmu->sets, mmu->ways, in arc_mmu_mumbojumbo()
680 * However for walking WAYS of a SET, we need to know this
682 #define SET_WAY_TO_IDX(mmu, set, way) ((set) * mmu->ways + (way))
687 * time of lookup matching multiple ways.
699 int set, n_ways = mmu->ways; in do_tlb_overlap_fault()
702 BUG_ON(mmu->ways > 4); in do_tlb_overlap_fault()
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/linux/drivers/cxl/
H A Dacpi.c33 /* No xormaps for host bridge interleave ways of 1 or 3 */ in cxl_xor_hpa_to_spa()
136 unsigned int ways; in cxl_acpi_cfmws_verify() local
155 rc = eiw_to_ways(cfmws->interleave_ways, &ways); in cxl_acpi_cfmws_verify()
157 dev_err(dev, "CFMWS Interleave Ways (%d) invalid\n", in cxl_acpi_cfmws_verify()
162 expected_len = struct_size(cfmws, interleave_targets, ways); in cxl_acpi_cfmws_verify()
351 unsigned int ways, i, ig; in DEFINE_FREE() local
358 rc = eiw_to_ways(cfmws->interleave_ways, &ways); in DEFINE_FREE()
364 for (i = 0; i < ways; i++) in DEFINE_FREE()
378 cxl_root_decoder_alloc(root_port, ways); in DEFINE_FREE()
390 cxld->interleave_ways = ways; in DEFINE_FREE()
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/linux/Documentation/devicetree/bindings/nios2/
H A Dnios2.txt23 - altr,tlb-num-ways: Specifies the number of set-associativity ways in the TLB.
52 altr,tlb-num-ways = <16>;
/linux/arch/powerpc/kvm/
H A De500_mmu.c42 if (unlikely(vcpu_e500->gtlb_nv[0] >= vcpu_e500->gtlb_params[0].ways)) in gtlb0_get_next_victim()
48 static int tlb0_set_base(gva_t addr, int sets, int ways) in tlb0_set_base() argument
53 set_base *= ways; in tlb0_set_base()
61 vcpu_e500->gtlb_params[0].ways); in gtlb0_set_base()
70 esel &= vcpu_e500->gtlb_params[0].ways - 1; in get_tlb_esel()
89 size = vcpu_e500->gtlb_params[0].ways; in kvmppc_e500_tlb_index()
358 esel &= vcpu_e500->gtlb_params[tlbsel].ways - 1; in kvmppc_e500_emul_tlbsx()
836 vcpu_e500->gtlb_params[0].ways = params.tlb_ways[0]; in kvm_vcpu_ioctl_config_tlb()
839 vcpu_e500->gtlb_params[1].ways = params.tlb_sizes[1]; in kvm_vcpu_ioctl_config_tlb()
876 vcpu->arch.tlbcfg[0] |= params[0].ways << TLBnCFG_ASSOC_SHIFT; in vcpu_mmu_init()
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H A De500_mmu_host.c730 host_tlb_params[0].ways = (mfspr(SPRN_TLB0CFG) & TLBnCFG_ASSOC) >> in e500_mmu_host_init()
732 host_tlb_params[1].ways = host_tlb_params[1].entries; in e500_mmu_host_init()
735 !is_power_of_2(host_tlb_params[0].ways) || in e500_mmu_host_init()
736 host_tlb_params[0].entries < host_tlb_params[0].ways || in e500_mmu_host_init()
737 host_tlb_params[0].ways == 0) { in e500_mmu_host_init()
738 pr_err("%s: bad tlb0 host config: %u entries %u ways\n", in e500_mmu_host_init()
740 host_tlb_params[0].ways); in e500_mmu_host_init()
745 host_tlb_params[0].entries / host_tlb_params[0].ways; in e500_mmu_host_init()
/linux/arch/arm/mm/
H A Dcache-l2x0.c42 static u32 l2x0_way_mask; /* Bitmask of active ways */
784 unsigned way_size_bits, ways; in __l2c_init() local
811 /* Determine the number of ways */ in __l2c_init()
817 ways = 16; in __l2c_init()
819 ways = 8; in __l2c_init()
824 ways = (aux >> 13) & 0xf; in __l2c_init()
828 ways = (aux >> 13) & 0xf; in __l2c_init()
829 ways = 2 << ((ways + 1) >> 2); in __l2c_init()
833 /* Assume unknown chips have 8 ways */ in __l2c_init()
834 ways = 8; in __l2c_init()
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/linux/arch/arm/include/asm/
H A Dshmparam.h6 * This should be the size of the virtually indexed cache/ways,
8 * every size/ways bytes.
/linux/arch/sh/include/asm/
H A Dcache.h27 unsigned int ways; /* Number of cache ways */ member

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