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/linux/Documentation/ABI/stable/
H A Dsysfs-driver-firmware-zynqmp1 What: /sys/devices/platform/firmware\:zynqmp-firmware/ggs*
11 The register is reset during system or power-on
17 # cat /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
18 # echo <value> > /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
22 # cat /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
23 # echo 0x1234ABCD > /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
27 What: /sys/devices/platform/firmware\:zynqmp-firmware/pggs*
38 This register is only reset by the power-on reset
46 # cat /sys/devices/platform/firmware\:zynqmp-firmware/pggs0
47 # echo <value> > /sys/devices/platform/firmware\:zynqmp-firmware/pggs0
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/linux/drivers/watchdog/
H A Dsmsc37b787_wdt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * SMsC 37B787 Watchdog Timer driver for Linux 2.6.x.x
9 * any of this software. This material is provided "AS-IS" in
12 * (C) Copyright 2003-2006 Sven Anders <anders@anduras.de>
15 * 2003 - Created version 1.0 for Linux 2.4.x.
16 * 2006 - Ported to Linux 2.6, added nowayout and MAGICCLOSE
21 * A Watchdog Timer (WDT) is a hardware circuit that can
26 * via the /dev/watchdog special device file that userspace is
28 * occurs, the driver will usually tell the hardware watchdog
29 * that everything is in order, and that the watchdog should wait
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H A Dstarfive-wdt.c1 // SPDX-License-Identifier: GPL-2.0
3 * Starfive Watchdog driver
15 #include <linux/watchdog.h>
17 /* JH7100 Watchdog register define */
31 /* JH7110 Watchdog register define */
35 * [0]: reset enable;
36 * [1]: interrupt enable && watchdog enable
56 #define STARFIVE_WDT_JH7100_INTCLR_AVA_SHIFT 1 /* Watchdog can clear interrupt when 0 */
74 MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (default="
77 "Watchdog is started at boot time if set to 1, default="
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H A Dpc87413_wdt.c1 // SPDX-License-Identifier: GPL-2.0+
3 * NS pc87413-wdt Watchdog Timer driver for Linux 2.6.x.x
12 * This material is provided "AS-IS" and at no charge.
22 #include <linux/watchdog.h>
42 #define DPFX MODNAME " - DEBUG: "
48 #define WDCTL 0x10 /* Watchdog-Timer-Control-Register */
49 #define WDTO 0x11 /* Watchdog timeout register */
50 #define WDCFG 0x12 /* Watchdog config register */
55 static int swc_base_addr = -1;
66 /* -- Low level function ----------------------------------------*/
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H A Dsa1100_wdt.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Watchdog driver for the SA11x0/PXA2xx
10 * "AS-IS" and at no charge.
27 #include <linux/watchdog.h>
40 #define REG_OWER 0x0018 /* OS timer Watch-dog Enable Reg. */
41 #define REG_OIER 0x001C /* OS timer Interrupt Enable Reg. */
48 #define OWER_WME (1 << 0) /* Watchdog Match Enable */
50 #define OIER_E3 (1 << 3) /* Interrupt enable channel 3 */
51 #define OIER_E2 (1 << 2) /* Interrupt enable channel 2 */
52 #define OIER_E1 (1 << 1) /* Interrupt enable channel 1 */
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H A Dat91sam9_wdt.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * drivers/watchdog/at91sam9_wdt.h
9 * Watchdog Timer (WDT) - System peripherals regsters.
20 #define AT91_WDT_CR 0x00 /* Watchdog Control Register */
24 #define AT91_WDT_MR 0x04 /* Watchdog Mode Register */
29 #define AT91_WDT_WDFIEN BIT(12) /* Fault Interrupt Enable */
30 #define AT91_SAM9X60_WDDIS BIT(12) /* Watchdog Disable */
33 #define AT91_WDT_WDDIS BIT(15) /* Watchdog Disable */
39 #define AT91_WDT_SR 0x08 /* Watchdog Status Register */
40 #define AT91_WDT_WDUNF BIT(0) /* Watchdog Underflow */
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H A Dvia_wdt.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * VIA Chipset Watchdog Driver
10 * Caveat: PnP must be enabled in BIOS to allow full access to watchdog
11 * control registers. If not, the watchdog must be configured in BIOS manually.
22 #include <linux/watchdog.h>
26 #define VIA_WDT_CONF 0xec /* watchdog enable state */
29 #define VIA_WDT_CONF_ENABLE 0x01 /* 1: enable watchdog */
30 #define VIA_WDT_CONF_MMIO 0x02 /* 1: enable watchdog MMIO */
33 * The MMIO region contains the watchdog control register and the
42 #define VIA_WDT_FIRED 0x02 /* 1: restarted by expired watchdog */
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H A Dcadence_wdt.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Cadence WDT driver - Used by Xilinx Zynq
5 * Copyright (C) 2010 - 2014 Xilinx, Inc.
18 #include <linux/watchdog.h>
21 /* Supports 1 - 516 sec */
54 "Watchdog time in seconds. (default="
59 "Watchdog cannot be stopped once started (default="
63 * struct cdns_wdt - Watchdog device structure
70 * @cdns_wdt_device: watchdog device structure
72 * Structure containing parameters specific to cadence watchdog.
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H A Dimx2_wdt.c1 // SPDX-License-Identifier: GPL-2.0
3 * Watchdog driver for IMX2 and later processors
11 * NOTE: MX1 has a slightly different Watchdog than MX2 and later:
14 * ---- -----
15 * Registers: 32-bit 16-bit
17 * Need to enable clk: No Yes
32 #include <linux/watchdog.h>
34 #define DRIVER_NAME "imx2-wdt"
37 #define IMX2_WDT_WCR_WT (0xFF << 8) /* -> Watchdog Timeout Field */
38 #define IMX2_WDT_WCR_WDW BIT(7) /* -> Watchdog disable for WAIT */
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H A Di6300esb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * i6300esb: Watchdog timer driver for Intel 6300ESB chipset
8 * based on i810-tco.c which is in turn based on softdog.c
12 * 6300ESB chip : document number 300641-004
21 * Change driver to use the watchdog subsystem
35 #include <linux/watchdog.h>
49 #define ESB_TIMER1_REG(w) ((w)->base + 0x00)/* Timer1 value after each reset */
50 #define ESB_TIMER2_REG(w) ((w)->base + 0x04)/* Timer2 value after each reset */
51 #define ESB_GINTSR_REG(w) ((w)->base + 0x08)/* General Interrupt Status Reg */
52 #define ESB_RELOAD_REG(w) ((w)->base + 0x0c)/* Reload register */
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H A Dcpwd.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* cpwd.c - driver implementation for hardware watchdog
5 * This device supports both the generic Linux watchdog
6 * interface and Solaris-compatible ioctls as best it is
38 #include <asm/watchdog.h>
42 #define WD_OBPNAME "watchdog"
43 #define WD_BADMODEL "SUNW,501-5336"
60 #define WD_STAT_INIT 0x01 /* Watchdog timer is initialized */
61 #define WD_STAT_BSTOP 0x02 /* Watchdog timer is brokenstopped */
62 #define WD_STAT_SVCD 0x04 /* Watchdog interrupt occurred */
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H A Drn5t618_wdt.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Watchdog driver for Ricoh RN5T618 PMIC
12 #include <linux/watchdog.h>
14 #define DRIVER_NAME "rn5t618-wdt"
20 MODULE_PARM_DESC(timeout, "Initial watchdog timeout in seconds");
23 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
33 * watchdog expiration times. If the watchdog is not accessed before
59 return -EINVAL; in rn5t618_wdt_set_timeout()
61 ret = regmap_update_bits(wdt->rn5t618->regmap, RN5T618_WATCHDOG, in rn5t618_wdt_set_timeout()
65 wdt_dev->timeout = rn5t618_wdt_map[i].time; in rn5t618_wdt_set_timeout()
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H A Dorion_wdt.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/watchdog/orion_wdt.c
5 * Watchdog driver for Orion/Kirkwood processors
18 #include <linux/watchdog.h>
30 #define INTERNAL_REGS_MASK ~(SZ_1M - 1)
33 * Watchdog timer block registers.
84 dev->clk = clk_get(&pdev->dev, NULL); in orion_wdt_clock_init()
85 if (IS_ERR(dev->clk)) in orion_wdt_clock_init()
86 return PTR_ERR(dev->clk); in orion_wdt_clock_init()
87 ret = clk_prepare_enable(dev->clk); in orion_wdt_clock_init()
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H A Dof_xilinx_wdt.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Watchdog Device Driver for Xilinx axi/xps_timebase_wdt
5 * (C) Copyright 2013 - 2014 Xilinx, Inc.
17 #include <linux/watchdog.h>
29 #define XWT_CSR0_EWDT1_MASK BIT(1) /* Enable bit 1 */
32 #define XWT_CSRX_EWDT2_MASK BIT(0) /* Enable bit 2 */
38 #define WATCHDOG_NAME "Xilinx Watchdog"
54 ret = clk_enable(xdev->clk); in xilinx_wdt_start()
56 dev_err(wdd->parent, "Failed to enable clock\n"); in xilinx_wdt_start()
60 spin_lock(&xdev->spinlock); in xilinx_wdt_start()
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H A Dftwdt010_wdt.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Watchdog driver for Faraday Technology FTWDT010
7 * Inspired by the out-of-tree drivers from OpenWRT:
20 #include <linux/watchdog.h>
54 u32 enable; in ftwdt010_enable() local
56 writel(timeout * WDT_CLOCK, gwdt->base + FTWDT010_WDLOAD); in ftwdt010_enable()
57 writel(WDRESTART_MAGIC, gwdt->base + FTWDT010_WDRESTART); in ftwdt010_enable()
59 enable = WDCR_CLOCK_5MHZ | WDCR_SYS_RST; in ftwdt010_enable()
60 writel(enable, gwdt->base + FTWDT010_WDCR); in ftwdt010_enable()
62 enable |= WDCR_WDINTR; in ftwdt010_enable()
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H A Dxilinx_wwdt.c1 // SPDX-License-Identifier: GPL-2.0
3 * Window watchdog device driver for Xilinx Versal WWDT
5 * Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc.
16 #include <linux/watchdog.h>
32 /* Enable and Status Register Masks */
50 "Watchdog time in seconds. (default="
54 "Watchdog closed window percentage. (default="
57 * struct xwwdt_device - Watchdog device structure
60 * @xilinx_wwdt_wdd: watchdog device structure
79 struct watchdog_device *xilinx_wwdt_wdd = &xdev->xilinx_wwdt_wdd; in xilinx_wwdt_start()
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H A Dstm32_iwdg.c1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for STM32 Independent Watchdog
22 #include <linux/watchdog.h>
32 #define IWDG_EWCR 0x14 /* Early Wake-up Register */
35 #define KR_KEY_RELOAD 0xAAAA /* reload counter enable */
36 #define KR_KEY_ENABLE 0xCCCC /* peripheral enable */
37 #define KR_KEY_EWA 0x5555 /* write access enable */
49 #define SR_PVU BIT(0) /* Watchdog prescaler value update */
50 #define SR_RVU BIT(1) /* Watchdog counter reload value update */
52 #define EWCR_EWIT GENMASK(11, 0) /* Watchdog counter window value */
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H A Dsp5100_tco.c1 // SPDX-License-Identifier: GPL-2.0-or-later
14 * AMD Publication 45482 "AMD SB800-Series Southbridges Register
17 * for AMD Family 16h Models 00h-0Fh Processors"
20 * for AMD Family 16h Models 30h-3Fh Processors"
21 * AMD Publication 55570-B1-PUB "Processor Programming Reference (PPR)
24 * AMD Publication 55772-A1-PUB "Processor Programming Reference (PPR)
43 #include <linux/watchdog.h>
47 #define TCO_DRIVER_NAME "sp5100-tco"
61 /* the watchdog platform device */
71 MODULE_PARM_DESC(action, "Action taken when watchdog expires, 0 to reset, 1 to poweroff (default="
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H A Dsbc8360.c1 // SPDX-License-Identifier: GPL-2.0+
3 * SBC8360 Watchdog driver
15 * (c) Copyright 2000-2001 Marek Michalkiewicz <marekm@linux.org.pl>
25 * "AS-IS" and at no charge.
29 * 14-Dec-2001 Matt Domsch <Matt_Domsch@dell.com>
40 #include <linux/watchdog.h>
58 * Watchdog Timer Configuration
60 * The function of the watchdog timer is to reset the system automatically
61 * and is defined at I/O port 0120H and 0121H. To enable the watchdog timer
64 * value to I/O port 0121H for the system to stop the watchdog function.
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H A Dmeson_wdt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Meson Watchdog Driver
20 #include <linux/watchdog.h>
38 unsigned int enable; member
44 .enable = BIT(22),
50 .enable = BIT(19),
67 tc_reboot |= meson_wdt->data->enable; in meson_wdt_restart()
70 writel(tc_reboot, meson_wdt->wdt_base + MESON_WDT_TC); in meson_wdt_restart()
81 writel(0, meson_wdt->wdt_base + MESON_WDT_RESET); in meson_wdt_ping()
92 reg = readl(meson_wdt->wdt_base + MESON_WDT_TC); in meson_wdt_change_timeout()
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H A DiTCO_vendor_support.c1 // SPDX-License-Identifier: GPL-2.0+
3 * intel TCO vendor specific watchdog driver support
5 * (c) Copyright 2006-2009 Wim Van Sebroeck <wim@iguana.be>.
9 * provided "AS-IS" and at no charge.
26 #include <linux/errno.h> /* For the -ENODEV/... values */
29 #include <linux/ioport.h> /* For io-port access */
35 /* SuperMicro Pentium 3 Era 370SSE+-OEM1/P3TSSE */
37 /* SuperMicro Pentium 4 / Xeon 4 / EMT64T Era Systems - no longer supported */
55 * Board: Super Micro Computer Inc. 370SSE+-OEM1/P3TSSE
61 * To enable Watchdog function:
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/linux/Documentation/devicetree/bindings/watchdog/
H A Datmel,sama5d4-wdt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/atmel,sama5d4-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Atmel SAMA5D4 Watchdog Timer (WDT) Controller
10 - Eugen Hristev <eugen.hristev@microchip.com>
13 - $ref: watchdog.yaml#
18 - enum:
19 - atmel,sama5d4-wdt
20 - microchip,sam9x60-wdt
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H A Dxlnx,xps-timebase-wdt.yaml1 # SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/watchdog/xlnx,xps-timebase-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx AXI/PLB softcore and window Watchdog Timer
10 - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
11 - Srinivas Neeli <srinivas.neeli@amd.com>
14 The Timebase watchdog timer(WDT) is a free-running 32 bit counter.
15 WDT uses a dual-expiration architecture. After one expiration of
22 - $ref: watchdog.yaml#
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/linux/tools/testing/selftests/watchdog/
H A Dwatchdog-test.c1 // SPDX-License-Identifier: GPL-2.0
3 * Watchdog Driver Test Program
4 * - Tests all ioctls
5 * - Tests Magic Close - CONFIG_WATCHDOG_NOWAYOUT
6 * - Could be tested against softdog driver on systems that
7 * don't have watchdog hardware.
8 * - TOD
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/linux/arch/mips/sibyte/swarm/
H A Drtc_m41t81.c1 // SPDX-License-Identifier: GPL-2.0-or-later
29 #define M41T81REG_HR_CEB 0x80 /* century enable bit */
33 #define M41T81REG_WD_RB0 0x01 /* watchdog resolution bit 0 */
34 #define M41T81REG_WD_RB1 0x02 /* watchdog resolution bit 1 */
35 #define M41T81REG_WD_BMB0 0x04 /* watchdog multiplier bit 0 */
36 #define M41T81REG_WD_BMB1 0x08 /* watchdog multiplier bit 1 */
37 #define M41T81REG_WD_BMB2 0x10 /* watchdog multiplier bit 2 */
38 #define M41T81REG_WD_BMB3 0x20 /* watchdog multiplier bit 3 */
39 #define M41T81REG_WD_BMB4 0x40 /* watchdog multiplier bit 4 */
40 #define M41T81REG_AMO_ABE 0x20 /* alarm in "battery back-up mode" enable bit */
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