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/linux/fs/
H A Dfs_pin.c1 // SPDX-License-Identifier: GPL-2.0
10 void pin_remove(struct fs_pin *pin) in pin_remove() argument
13 hlist_del_init(&pin->m_list); in pin_remove()
14 hlist_del_init(&pin->s_list); in pin_remove()
16 spin_lock_irq(&pin->wait.lock); in pin_remove()
17 pin->done = 1; in pin_remove()
18 wake_up_locked(&pin->wait); in pin_remove()
19 spin_unlock_irq(&pin->wait.lock); in pin_remove()
22 void pin_insert(struct fs_pin *pin, struct vfsmount *m) in pin_insert() argument
25 hlist_add_head(&pin->s_list, &m->mnt_sb->s_pins); in pin_insert()
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/linux/arch/arm/boot/dts/samsung/
H A Dexynos5250-snow-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/maxim,max77686.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/sound/samsung-i2s.h>
30 stdout-path = "serial3:115200n8";
33 gpio-keys {
34 compatible = "gpio-keys";
35 pinctrl-names = "default";
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/linux/rust/kernel/sync/
H A Dcondvar.rs1 // SPDX-License-Identifier: GPL-2.0
18 use core::{marker::PhantomPinned, pin::Pin, ptr};
21 /// Creates a [`CondVar`] initialiser with the given name and a newly-created lock class.
50 /// #[pin]
53 /// #[pin]
61 /// e.value_changed.wait(&mut guard);
72 /// fn new_example() -> Result<Pin<KBox<Example>>> {
74 /// value <- new_mutex!(0),
75 /// value_changed <- new_condvar!(),
80 /// [`struct wait_queue_head`]: srctree/include/linux/wait.h
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H A Dcompletion.rs1 // SPDX-License-Identifier: GPL-2.0
14 /// waking up other tasks that have been queued up to wait for the [`Completion`] to be completed.
24 /// #[pin]
26 /// #[pin]
35 /// fn new() -> Result<Arc<Self>> {
37 /// work <- new_work!("MyTask::work"),
38 /// done <- Completion::new(),
68 #[pin]
80 pub fn new() -> impl PinInit<Self> { in new()
82 inner <- Opaque::ffi_init(|slot: *mut bindings::completion| { in new()
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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dlantiq,pinctrl-xway.txt4 - compatible: "lantiq,<chip>-pinctrl", where <chip> is:
10 - reg: Should contain the physical address and length of the gpio/pinmux
13 Please refer to pinctrl-bindings.txt in this directory for details of the
15 phrase "pin configuration node".
17 Lantiq's pin configuration nodes act as a container for an arbitrary number of
19 pin, a group, or a list of pins or groups. This configuration can include the
20 mux function to select on those group(s), and two pin configuration parameters:
21 pull-up and open-drain
27 other words, a subnode that lists a mux function but no pin configuration
28 parameters implies no information about any pin configuration parameters.
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/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dti,gpmc-child.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ti,gpmc-child.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
11 - Roger Quadros <rogerq@kernel.org>
24 gpmc,sync-clk-ps:
28 # Chip-select signal timings corresponding to GPMC_CONFIG2:
29 gpmc,cs-on-ns:
33 gpmc,cs-rd-off-ns:
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H A Dti,gpmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ti,gpmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
11 - Roger Quadros <rogerq@kernel.org>
16 - Asynchronous SRAM-like memories and ASICs
17 - Asynchronous, synchronous, and page mode burst NOR flash
18 - NAND flash
19 - Pseudo-SRAM devices
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/linux/tools/testing/selftests/mm/
H A Dcow.c1 // SPDX-License-Identifier: GPL-2.0-only
21 #include <sys/wait.h>
72 for (; size; addr += pagesize, size -= pagesize) in range_is_swapped()
85 if (pipe(comm_pipes->child_ready) < 0) { in setup_comm_pipes()
87 return -errno; in setup_comm_pipes()
89 if (pipe(comm_pipes->parent_ready) < 0) { in setup_comm_pipes()
91 close(comm_pipes->child_ready[0]); in setup_comm_pipes()
92 close(comm_pipes->child_ready[1]); in setup_comm_pipes()
93 return -errno; in setup_comm_pipes()
101 close(comm_pipes->child_ready[0]); in close_comm_pipes()
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/linux/drivers/mtd/nand/raw/
H A Dnand_legacy.c1 // SPDX-License-Identifier: GPL-2.0
4 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
23 * nand_read_byte - [DEFAULT] read one byte from the chip
30 return readb(chip->legacy.IO_ADDR_R); in nand_read_byte()
34 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
42 return (uint8_t) cpu_to_le16(readw(chip->legacy.IO_ADDR_R)); in nand_read_byte16()
46 * nand_select_chip - [DEFAULT] control CE line
48 * @chipnr: chipnumber to select, -1 for deselect
55 case -1: in nand_select_chip()
56 chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE, in nand_select_chip()
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/linux/rust/pin-init/
H A DREADME.md1 [![Crates.io](https://img.shields.io/crates/v/pin-init.svg)](https://crates.io/crates/pin-init)
2 [![Documentation](https://docs.rs/pin-init/badge.svg)](https://docs.rs/pin-init/)
3 [![Dependency status](https://deps.rs/repo/github/Rust-for-Linu
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/linux/drivers/md/bcache/
H A Djournal.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 * The journal is treated as a circular buffer of buckets - a journal entry
16 * superblock - all the things that are frequently updated. This is for future
22 * Currently, we don't journal BTREE_REPLACE operations - this will hopefully be
23 * fixed eventually. This isn't a bug - BTREE_REPLACE is used for insertions
32 * journal entry still open - i.e. that has keys that haven't been flushed to
38 * zero, we pop it off - thus, the size of the fifo tells us the number of open
48 * might contain keys for many journal entries - we handle this by making sure
56 * last_seq - the oldest journal entry we still need. We write last_seq in each
61 * newest journal entry it contains - if we don't need that journal entry we
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H A Dalloc.c1 // SPDX-License-Identifier: GPL-2.0
10 * btree pointers - they must match for the pointer to be considered valid.
19 * When we invalidate a bucket, we have to write its new gen to disk and wait
20 * for that write to complete before we use it - otherwise after a crash we
29 * free_inc isn't the only freelist - if it was, we'd often to sleep while
30 * priorities and gens were being written before we could allocate. c->free is a
37 * have nothing pointing into them - these we can reuse without waiting for
40 * them (because they were overwritten). That's the unused list - buckets on the
43 * It's also important to ensure that gens don't wrap around - with respect to
45 * difficult to do in practice, but we explicitly guard against it anyways - if
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/linux/fs/xfs/
H A Dxfs_dquot_item.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2000-2003 Silicon Graphics, Inc.
55 qlf->qlf_type = XFS_LI_DQUOT; in xfs_qm_dquot_logitem_format()
56 qlf->qlf_size = 2; in xfs_qm_dquot_logitem_format()
57 qlf->qlf_id = qlip->qli_dquot->q_id; in xfs_qm_dquot_logitem_format()
58 qlf->qlf_blkno = qlip->qli_dquot->q_blkno; in xfs_qm_dquot_logitem_format()
59 qlf->qlf_len = 1; in xfs_qm_dquot_logitem_format()
60 qlf->qlf_boffset = qlip->qli_dquot->q_bufoffset; in xfs_qm_dquot_logitem_format()
63 xfs_dquot_to_disk(&ddq, qlip->qli_dquot); in xfs_qm_dquot_logitem_format()
70 * Increment the pin count of the given dquot.
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/linux/Documentation/devicetree/bindings/sound/
H A Dcirrus,cs42l42.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - patches@opensource.cirrus.com
13 The CS42L42 is a low-power audio codec designed for portable applications.
14 It provides a high-dynamic range, stereo DAC for audio playback and a mono
15 high-dynamic-range ADC for audio capture. There is an integrated headset
21 - cirrus,cs42l42
22 - cirrus,cs42l83
29 VP-supply:
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/linux/include/uapi/linux/
H A Dserial.h1 /* SPDX-License-Identifier: GPL-1.0+ WITH Linux-syscall-note */
33 unsigned short closing_wait; /* time to wait before closing */
42 * For the close wait times, 0 means wait forever for serial port to
43 * flush its output. 65535 means don't wait at all.
64 #define PORT_RSA 13 /* RSA-DV II/S card */
83 * Multiport serial configuration structure --- external structure
100 * Serial input interrupt line counters -- external structure
112 * struct serial_rs485 - serial interface for controlling RS485 settings.
133 * * %SER_RS485_ENABLED - RS485 enabled.
134 * * %SER_RS485_RTS_ON_SEND - Logical level for RTS pin when sending.
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/linux/include/sound/
H A Dsoc-jack.h1 /* SPDX-License-Identifier: GPL-2.0
3 * soc-jack.h
12 * struct snd_soc_jack_pin - Describes a pin to update based on jack detection
14 * @pin: name of the pin to update
16 * @invert: if non-zero then pin is enabled when status is not reported
21 const char *pin; member
27 * struct snd_soc_jack_zone - Describes voltage zones of jack detection
32 * @debounce_time: debounce_time for jack, codec driver should wait for this
45 * struct snd_soc_jack_gpio - Describes a gpio pin for jack detection
/linux/drivers/memory/
H A Domap-gpmc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2005-2006 Nokia Corporation
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
33 #include <linux/omap-gpmc.h>
37 #include <linux/platform_data/mtd-nand-omap2.h>
39 #define DEVICE_NAME "omap-gpmc"
138 #define GPMC_CONFIG_WAITPINPOLARITY(pin) (BIT(pin) << 8) argument
235 u32 pin; member
258 /* Define chip-selects as reserved by default until probe completes */
306 * gpmc_get_clk_period - get period of selected clock domain in ps
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/linux/Documentation/driver-api/media/
H A Dcec-core.rst1 .. SPDX-License-Identifier: GPL-2.0
15 ----------------
33 ---------------------
53 will be stored in adap->priv and can be used by the adapter ops.
95 Implementing the Low-Level CEC Adapter
96 --------------------------------------
98 The following low-level adapter operations have to be implemented in
103 .. code-block:: none
107 /* Low-level callbacks */
123 /* High-level callback */
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/linux/arch/sh/boards/
H A Dboard-magicpanelr2.c1 // SPDX-License-Identifier: GPL-2.0
35 /* Wait until reset finished. Timeout is 100ms. */
65 /* CS2: LAN (0x08000000 - 0x0bffffff) */ in setup_chip_select()
68 /* (SW:1.5 WR:3 HW:1.5), ext. wait */ in setup_chip_select()
71 /* CS4: CAN1 (0xb0000000 - 0xb3ffffff) */ in setup_chip_select()
74 /* (SW:1.5 WR:3 HW:1.5), ext. wait */ in setup_chip_select()
77 /* CS5a: CAN2 (0xb4000000 - 0xb5ffffff) */ in setup_chip_select()
80 /* (SW:1.5 WR:3 HW:1.5), ext. wait */ in setup_chip_select()
83 /* CS5b: CAN3 (0xb6000000 - 0xb7ffffff) */ in setup_chip_select()
86 /* (SW:1.5 WR:3 HW:1.5), ext. wait */ in setup_chip_select()
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/linux/virt/kvm/
H A Deventfd.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * kvm eventfd support - use eventfd objects to signal various KVM events
17 #include <linux/wait.h>
46 struct kvm *kvm = irqfd->kvm; in irqfd_inject()
48 if (!irqfd->resampler) { in irqfd_inject()
49 kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, irqfd->gsi, 1, in irqfd_inject()
51 kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, irqfd->gsi, 0, in irqfd_inject()
55 irqfd->gsi, 1, false); in irqfd_inject()
62 list_for_each_entry_srcu(irqfd, &resampler->list, resampler_link, in irqfd_resampler_notify()
63 srcu_read_lock_held(&resampler->kvm->irq_srcu)) in irqfd_resampler_notify()
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/linux/include/linux/
H A Dwm97xx.h1 /* SPDX-License-Identifier: GPL-2.0 */
62 #define WM97XX_SLT(i) ((i - 5) & 0x7) /* panel slot (5-11) */
71 #define WM9712_45W 0x1000 /* set for 5-wire touchscreen */
73 #define WM9712_WAIT 0x0200 /* wait until adc is read before next sample */
75 #define WM9712_MASK_HI 0x0040 /* hi on mask pin (47) stops conversions */
76 #define WM9712_MASK_EDGE 0x0080 /* rising/falling edge on pin delays sample */
90 #define WM9705_WAIT 0x0100 /* wait until adc is read before next sample */
94 #define WM9705_MASK_EDGE 0x0020 /* rising/falling edge on pin delays sample */
110 #define WM9713_WAIT 0x0200 /* coordinate wait */
146 /*---------------- Return codes from sample reading functions ---------------*/
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/linux/include/linux/platform_data/
H A Dgpmc-omap.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2014 Texas Instruments, Inc. - https://www.ti.com
34 /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
59 u32 access; /* Start-cycle to first data valid delay */
134 #define GPMC_DEVWIDTH_8BIT 1 /* 8-bit device width */
135 #define GPMC_DEVWIDTH_16BIT 2 /* 16-bit device width */
136 #define GPMC_MUX_AAD 1 /* Addr-Addr-Data multiplex */
137 #define GPMC_MUX_AD 2 /* Addr-Data multiplex */
139 /* Wait pin polarity values */
153 bool wait_on_read; /* monitor wait on reads */
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/linux/rust/kernel/
H A Ddevres.rs1 // SPDX-License-Identifier: GPL-2.0
25 #[pin]
28 #[pin]
31 #[pin]
66 /// unsafe fn new(paddr: usize) -> Result<Self>{
88 /// fn deref(&self) -> &Self::Target {
93 /// # fn no_run(dev: &Device<Bound>) -> Result<(), Error> {
106 /// `Self::inner` is guaranteed to be initialized and is always accessed read-only.
120 #[pin]
133 ) -> impl PinInit<Self, Error> + 'a in new()
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/linux/Documentation/devicetree/bindings/power/reset/
H A Dgpio-restart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/reset/gpio-restart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sebastian Reichel <sre@kernel.org>
17 'open-source' is not found, the GPIO line will be driven in the inactive state. Otherwise its
22 This will also cause an inactive->active edge condition, triggering positive edge triggered
23 reset. After a delay specified by active-delay, the GPIO is set to inactive, thus causing an
24 active->inactive edge, triggering negative edge triggered reset. After a delay specified by
25 inactive-delay, the GPIO is driven active again. After a delay specified by wait-delay, the
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/linux/drivers/pinctrl/
H A Dpinctrl-xway.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/drivers/pinctrl/pinmux-xway.c
4 * based on linux/drivers/pinctrl/pinmux-pxa910.c
21 #include "pinctrl-lantiq.h"
31 /* we have 2 mux bits that can be set for each pin */
66 .pin = a, \
110 /* --------- ase related code --------- */
114 /* pin f0 f1 f2 f3 */
238 /* --------- danube related code --------- */
242 /* pin f0 f1 f2 f3 */
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