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/freebsd/sys/contrib/device-tree/Bindings/w1/
H A Dw1-gpio.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/w1/w1-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Bitbanged GPIO 1-Wire Bus
10 - Daniel Mack <zonque@gmail.com>
14 const: w1-gpio
19 - description: Data I/O pin
20 - description: Enable pin for an external pull-up resistor
22 linux,open-drain:
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H A Dw1-gpio.txt1 w1-gpio devicetree bindings
5 - compatible: "w1-gpio"
6 - gpios: one or two GPIO specs:
7 - the first one is used as data I/O pin
8 - the second one is optional. If specified, it is used as
13 - linux,open-drain: if specified, the data pin is considered in
14 open-drain mode.
16 Also refer to the generic w1.txt document.
21 compatible = "w1-gpio";
22 gpios = <&gpio 0 GPIO_ACTIVE_HIGH>;
H A Dw1.txt1 Generic devicetree bindings for onewire (w1) busses
5 Slave devices are listed as sub-nodes of such master devices. For now, only
12 compatible = "gpio-charger";
13 charger-type = "mains";
14 gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
18 compatible = "w1-gpio";
19 gpios = <&gpio 100 0>, <&gpio 101 0>;
23 power-supplies = <&charger>;
/freebsd/sys/contrib/device-tree/src/arm/intel/pxa/
H A Dpxa300-raumfeld-controller.dts1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include "pxa300-raumfeld-common.dtsi"
9 compatible = "raumfeld,raumfeld-controller-pxa303", "marvell,pxa300";
11 reg_vbatt: regulator-vbatt {
12 compatible = "regulator-fixed";
13 regulator-name = "vbatt-fixed-supply";
14 regulator-min-microvolt = <3700000>;
15 regulator-max-microvolt = <3700000>;
16 regulator-always-on;
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/freebsd/sys/contrib/device-tree/src/arm/aspeed/
H A Daspeed-bmc-opp-zaius.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
3 #include "aspeed-g5.dtsi"
4 #include <dt-bindings/gpio/aspeed-gpio.h>
8 compatible = "ingrasys,zaius-bmc", "aspeed,ast2500";
19 stdout-path = &uart5;
27 reserved-memory {
28 #address-cells = <1>;
29 #size-cells = <1>;
33 no-map;
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/freebsd/sys/contrib/device-tree/src/arm/nxp/mxs/
H A Dimx28-cfa10049.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * The CFA-10049 is an expansion board for the CFA-10036 module, thus we
8 * need to include the CFA-10036 DTS.
10 #include "imx28-cfa10036.dts"
13 model = "Crystalfontz CFA-1004
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H A Dimx28-tx28.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
4 * Copyright 2013-2017 Lothar Waßmann <LW@KARO-electronics.de>
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
13 model = "Ka-Ro electronics TX28 module";
34 reg = <0x40000000 0>; /* will be filled in by U-Boot */
38 compatible = "w1-gpio";
43 reg_usb0_vbus: regulator-usb0-vbus {
44 compatible = "regulator-fixed";
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/freebsd/share/man/man4/
H A Dowc.429 .Nd Dallas Semiconductor 1-Wire Controller
35 module implements Dallas Semiconductor 1-Wire signaling.
38 driver 1-Wire bus protocol.
41 device implements the Link Layer of the 1-Wire bus protocol stack.
47 Strong pull-up functionality needed to support parasitic mode is not
50 To enable 1-Wire for FDT systems requires modifying the DTS for your
52 .Bd -literal
56 compatible = "w1-gpio";
57 gpios = <&gpio 4 1>;
63 The gpios property describes the GPIO pin the 1-Wire bus is connected
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/freebsd/sys/contrib/device-tree/src/arm/microchip/
H A Dat91-ariag25.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * at91-ariag25.dts - Device Tree file for Acme Systems Aria G25 (AT91SAM9G25 based)
8 /dts-v1/;
32 clock-frequency = <32768>;
36 clock-frequency = <12000000>;
41 compatible = "gpio-leds";
47 linux,default-trigger = "heartbeat";
53 compatible = "w1-gpio";
55 pinctrl-names = "default";
56 pinctrl-0 = <&pinctrl_w1_0>;
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H A Dat91sam9x5cm.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * at91sam9x5cm.dtsi - Device Tree Include file for AT91SAM9x5 CPU Module
16 clock-frequency = <32768>;
20 clock-frequency = <12000000>;
28 compatible = "atmel,tcb-timer";
33 compatible = "atmel,tcb-timer";
40 pinctrl_1wire_cm: 1wire_cm-0 {
52 pinctrl-0 = <&pinctrl_ebi_addr_nand
54 pinctrl-names = "default";
57 nand_controller: nand-controller {
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/freebsd/sys/dev/sound/pci/hda/
H A Dhdaa.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
6 * Copyright (c) 2008-2012 Alexander Motin <mav@FreeBSD.org>
50 #define hdaa_lock(devinfo) snd_mtxlock((devinfo)->lock)
51 #define hdaa_unlock(devinfo) snd_mtxunlock((devinfo)->lock)
52 #define hdaa_lockassert(devinfo) snd_mtxassert((devinfo)->lock)
82 static const char *HDA_DEVS[16] = {"Line-out", "Speaker", "Headphones", "CD",
83 "SPDIF-out", "Digital-out", "Modem-line", "Modem-handset", "Line-in",
84 "AUX", "Mic", "Telephony", "SPDIF-in", "Digital-in", "Res.E", "Other"};
90 "DIN", "XLR", "RJ-11", "Combo", "0xc", "0xd", "0xe", "Other" };
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/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx6ul-imx6ull-opos6uldev.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 stdout-path = &uart1;
11 compatible = "pwm-backlight";
13 brightness-levels = <0 4 8 16 32 64 128 255>;
14 default-brightness-level = <7>;
15 power-supply = <&reg_5v>;
19 gpio-keys {
20 compatible = "gpio-keys";
21 pinctrl-names = "default";
22 pinctrl-0 = <&pinctrl_gpio_keys>;
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/freebsd/sys/contrib/device-tree/src/arm/allwinner/
H A Dsun5i-r8-chip.dts5 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 * This file is dual-licensed: you can use it either under the terms
46 /dts-v1/;
47 #include "sun5i-r8.dtsi"
48 #include "sunxi-common-regulators.dtsi"
50 #include <dt-bindings/gpio/gpio.h>
51 #include <dt-bindings/interrupt-controller/irq.h>
55 compatible = "nextthing,chip", "allwinner,sun5i-r8", "allwinner,sun5i-a13";
67 stdout-path = "serial0:115200n8";
71 compatible = "gpio-leds";
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/freebsd/sys/contrib/device-tree/src/arm/intel/ixp/
H A Dintel-ixp42x-arcom-vulcan.dts1 // SPDX-License-Identifier: ISC
8 /dts-v1/;
10 #include "intel-ixp42x.dtsi"
11 #include <dt-bindings/input/input.h>
16 #address-cells = <1>;
17 #size-cells = <1>;
27 stdout-path = "uart0:115200n8";
35 compatible = "w1-gpio";
42 compatible = "intel,ixp4xx-flash", "cfi-flash";
43 bank-width = <2>;
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/freebsd/sys/contrib/device-tree/src/arm64/amlogic/
H A Dmeson-axg-jethome-jethub-j1xx.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
10 /dts-v1/;
12 #include "meson-axg.dtsi"
13 #include <dt-bindings/input/input.h>
14 #include <dt-bindings/thermal/thermal.h>
24 stdout-path = "serial0:115200n8";
27 reserved-memory {
33 emmc_pwrseq: emmc-pwrseq {
34 compatible = "mmc-pwrseq-emmc";
35 reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
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/freebsd/sys/dev/ow/
H A Dowc_gpiobus.c1 /*-
32 #include <sys/gpio.h>
39 #include <dev/gpio/gpiobusvar.h>
47 {"w1-gpio", true},
56 #define OWC_GPIOBUS_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
57 #define OWC_GPIOBUS_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
59 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \
61 #define OWC_GPIOBUS_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx);
88 ofw_bus_search_compatible(dev, compat_data)->ocd_data) in owc_gpiobus_probe()
92 device_set_desc(dev, "GPIO one-wire bus"); in owc_gpiobus_probe()
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/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-am642-phyboard-electra-rdk.dts1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * Copyright (C) 2021-2024 PHYTEC America, LLC - https://www.phytec.com
6 * Copyright (C) 2022-2024 PHYTEC Messtechnik GmbH
10 * https://www.phytec.com/product/phyboard-am64x
13 /dts-v1/;
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/input/input.h>
17 #include <dt-bindings/leds/common.h>
18 #include <dt-bindings/leds/leds-pca9532.h>
19 #include <dt-bindings/phy/phy.h>
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H A Dk3-am654-idk.dtso1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2018-2024 Texas Instruments Incorporated - https://www.ti.com/
8 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/net/ti-dp83867.h>
13 #include "k3-pinctrl.h"
17 ethernet3 = "/icssg0-eth/ethernet-ports/port@0";
18 ethernet4 = "/icssg0-eth/ethernet-ports/port@1";
19 ethernet5 = "/icssg1-eth/ethernet-ports/port@0";
20 ethernet6 = "/icssg1-eth/ethernet-ports/port@1";
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H A Dk3-am62x-sk-common.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/leds/common.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/net/ti-dp83867.h>
11 #include "k3-am625.dtsi"
27 stdout-path = "serial2:115200n8";
31 bootph-pre-ram;
37 reserved-memory {
38 #address-cells = <2>;
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H A Dk3-am642-tqma64xxl-mbax4xxl.dts1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
4 * Copyright (c) 2022-2024 TQ-Systems GmbH <linux@ew.tq-group.com>, D-82229 Seefeld, Germany.
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/net/ti-dp83867.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/pwm/pwm.h>
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/freebsd/sys/gnu/dev/bwn/phy_n/
H A Dif_bwn_phy_n_regs.h22 Boston, MA 02110-1301, USA.
32 /* N-PHY registers. */
41 #define BWN_NPHY_4WI_ADDR BWN_PHY_N(0x00B) /* Four-wire bus address */
42 #define BWN_NPHY_4WI_DATAHI BWN_PHY_N(0x00C) /* Four-wire bus data high */
43 #define BWN_NPHY_4WI_DATALO BWN_PHY_N(0x00D) /* Four-wire bus data low */
44 #define BWN_NPHY_BIST_STAT0 BWN_PHY_N(0x00E) /* Built-in self test status 0 */
45 #define BWN_NPHY_BIST_STAT1 BWN_PHY_N(0x00F) /* Built-in self test status 1 */
98 #define BWN_NPHY_C1_W1THRES BWN_PHY_N(0x028) /* Core 1 W1 threshold */
156 #define BWN_NPHY_C2_W1THRES BWN_PHY_N(0x03E) /* Core 2 W1 threshold */
201 #define BWN_NPHY_W1CLIP1_DWELL_LEN BWN_PHY_N(0x06D) /* W1 clip1 dwell length */
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/freebsd/sys/contrib/dev/rtw89/
H A Dcoex.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2020 Realtek Corporation
213 #define RTW89_DEFAULT_BTC_VER_IDX (ARRAY_SIZE(rtw89_btc_ver_defs) - 1)
435 /* TDMA off + pri: WL_Hi-Tx > BT_Hi_Rx, BT_Hi > WL > BT_Lo */
438 /* TDMA off + pri: WL_Hi-Tx > BT, BT_Hi > other-W
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H A Dcore.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Realtek Corporation
50 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI)
107 RTW89_CH_6G_BAND_IDX6, /* Ultra-high */
108 RTW89_CH_6G_BAND_IDX7, /* Ultra-high */
256 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 -
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/freebsd/sys/dev/qlnx/qlnxe/
H A Dreg_addr.h2 * Copyright (c) 2017-2018 Cavium, Inc.
78 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl…
79 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea…
80 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn…
81 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea…
88 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of …
90 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
116 … (0x1<<9) // Fast back-to-back transaction ena…
128 … (0x1<<23) // Fast back-to-back capable. Not ap…
145 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
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