Home
last modified time | relevance | path

Searched +full:vsync +full:- +full:polarity +full:- +full:high (Results 1 – 25 of 45) sorted by relevance

12

/linux/Documentation/fb/
H A Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
25 # Polarity negative negative
28 mode "640x480-60"
31 timings 39722 48 16 33 10 96 2 endmode mode "480x640-60"
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
50 # Polarity negative negative
52 mode "640x480-75"
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
71 # Polarity negative negative
73 mode "640x480-85"
[all …]
H A Dpxafb.rst10 modprobe pxafb options=vmem:2M,mode:640x480-8,passive
14 video=pxafb:vmem:2M,mode:640x480-8,passive
21 mode:XRESxYRES[-BPP]
45 vsynclen:VSYNC == LCCR2_VSW + 1
65 hsync:HSYNC, vsync:VSYNC
68 high.
74 outputen:POLARITY
76 Output Enable Polarity. 0 => active low, 1 => active high
78 pixclockpol:POLARITY
80 pixel clock polarity
[all …]
H A Dmatroxfb.rst16 * Most important: boot logo :-)
34 box) and matroxfb (for graphics mode). You should not compile-in vesafb
35 unless you have primary display on non-Matrox VBE2.0 device (see
43 -------------
58 -------------------------
73 ----------
86 Non-listed number can be achieved by more complicated command-line, for
93 XF{68,86}_FBDev should work just fine, but it is non-accelerated. On non-intel
97 Running another (accelerated) X-Server like XF86_SVGA works too. But (at least)
100 driver is possible, but you must not enable DRI - if you do, resolution and
[all …]
/linux/Documentation/devicetree/bindings/regulator/
H A Drichtek,rtmv20-regulator.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/regulator/richtek,rtmv20-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - ChiYuan Huang <cy_huang@richtek.com>
16 There're still four pins for camera control, two inputs (strobe and vsync),
18 supply, vsync input from IR camera, and fsin1/fsin2 output for the optional.
27 wakeup-source: true
32 enable-gpios:
36 richtek,ld-pulse-delay-us:
[all …]
/linux/include/media/i2c/
H A Dtvp7002.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* Texas Instruments Triple 8-/10-BIT 165-/110-MSPS Video and Graphics
6 * Author: Santiago Nunez-Corrales <santiago.nunez@ridgerun.com>
19 * struct tvp7002_config - Platform dependent data
20 *@clk_polarity: Clock polarity
21 * 0 - Data clocked out on rising edge of DATACLK signal
22 * 1 - Data clocked out on falling edge of DATACLK signal
23 *@hs_polarity: HSYNC polarity
24 * 0 - Active low HSYNC output, 1 - Active high HSYNC output
25 *@vs_polarity: VSYNC Polarity
[all …]
/linux/arch/sh/include/asm/
H A Dsh7760fb.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sh7760fb.h -- platform data for SH7760/SH7763 LCDC framebuffer driver.
5 * (c) 2006-2008 MSC Vertriebsges.m.b.H.,
19 /* The LCDC dma engine always sets bits 27-26 to 1: this is Area3 */
75 /* HSYNC polarity inversion */
78 /* VSYNC polarity inversion */
81 /* DISPLAY-ENABLE polarity inversion */
84 /* DISPLAY DATA BUS polarity inversion */
90 /* Disable output of HSYNC during VSYNC period */
93 /* Disable output of VSYNC during VSYNC period */
[all …]
/linux/Documentation/devicetree/bindings/media/i2c/
H A Dtvp7002.txt7 - compatible : Must be "ti,tvp7002"
10 - hsync-active: HSYNC Polarity configuration for the bus. Default value when
13 - vsync-active: VSYNC Polarity configuration for the bus. Default value when
16 - pclk-sample: Clock polarity of the bus. Default value when this property is
19 - sync-on-green-active: Active state of Sync-on-green signal property of the
24 - field-even-active: Active-high Field ID output polarity control of the bus.
28 1 = FID output polarity inverted
31 video-interfaces.txt.
44 hsync-active = <1>;
45 vsync-active = <1>;
[all …]
H A Dtvp514x.txt3 The TVP5146/TVP5146m2/TVP5147/TVP5147m1 device is high quality, single-chip
5 video formats into digital video component. The tvp514x decoder supports analog-
6 to-digital (A/D) conversion of component RGB and YPbPr signals as well as A/D
7 conversion and decoding of NTSC, PAL and SECAM composite and S-video into
11 - compatible : value should be either one among the following
17 - hsync-active: HSYNC Polarity configuration for endpoint.
19 - vsync-active: VSYNC Polarity configuration for endpoint.
21 - pclk-sample: Clock polarity of the endpoint.
24 media/video-interfaces.txt.
37 hsync-active = <1>;
[all …]
H A Dtda1997x.txt1 Device-Tree bindings for the NXP TDA1997x HDMI receiver
6 - RGB 8bit per color (24 bits total): R[11:4] B[11:4] G[11:4]
7 - YUV444 8bit per color (24 bits total): Y[11:4] Cr[11:4] Cb[11:4]
8 - YUV422 semi-planar 8bit per component (16 bits total): Y[11:4] CbCr[11:4]
9 - YUV422 semi-planar 10bit per component (20 bits total): Y[11:2] CbCr[11:2]
10 - YUV422 semi-planar 12bit per component (24 bits total): - Y[11:0] CbCr[11:0]
11 - YUV422 BT656 8bit per component (8 bits total): YCbCr[11:4] (2-cycles)
12 - YUV422 BT656 10bit per component (10 bits total): YCbCr[11:2] (2-cycles)
13 - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles)
16 - RGB 12bit per color (36 bits total): R[11:0] B[11:0] G[11:0]
[all …]
/linux/Documentation/admin-guide/media/
H A Dmgb4.rst1 .. SPDX-License-Identifier: GPL-2.0
7 ---------------
13 There are two types of parameters - global / PCI card related, found under
23 | 0 - No module present
24 | 1 - FPDL3
25 | 2 - GMSL
33 | 1 - FPDL3
34 | 2 - GMSL
42 PRODUCT-REVISION-SERIES-SERIAL
55 | 0 - single
[all …]
/linux/Documentation/devicetree/bindings/display/samsung/
H A Dsamsung,exynos5-dp.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/samsung/samsung,exynos5-dp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Inki Dae <inki.dae@samsung.com>
11 - Seung-Woo Kim <sw0312.kim@samsung.com>
12 - Kyungmin Park <kyungmin.park@samsung.com>
13 - Krzysztof Kozlowski <krzk@kernel.org>
17 const: samsung,exynos5-dp
25 clock-names:
[all …]
/linux/include/media/
H A Dv4l2-mediabus.h1 /* SPDX-License-Identifier: GPL-2.0-only */
11 #include <linux/v4l2-mediabus.h>
46 * Signal polarity flags
47 * Note: in BT.656 mode HSYNC, FIELD, and VSYNC are unused
60 /* FIELD = 0/1 - Field1 (odd)/Field2 (even) */
62 /* FIELD = 1/0 - Field1 (odd)/Field2 (even) */
64 /* Active state of Sync-o
[all...]
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc_hw_types.h41 * Note: do *not* add any types which are *not* used for HW programming - this
245 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such
395 * 0x0 - DISPLAY_MICRO_TILING
396 * 0x1 - THIN_MICRO_TILING
397 * 0x2 - DEPTH_MICRO_TILING
398 * 0x3 - ROTATED_MICRO_TILING
560 * enum dc_cursor_color_format - DC cursor programming mode
600 * divided into a high and low parts.
781 it is positive polarity --reversed with dal1 or video bios define*/
783 it is positive polarity --reversed with dal1 or video bios define*/
[all …]
/linux/drivers/media/i2c/
H A Dtda1997x.c1 // SPDX-License-Identifier: GPL-2.0
16 #include <linux/v4l2-dv-timings.h>
19 #include <media/v4l2-ctrls.h>
20 #include <media/v4l2-device.h>
21 #include <media/v4l2-dv-timings.h>
22 #include <media/v4l2-event.h>
23 #include <media/v4l2-fwnode.h>
31 #include <dt-bindings/media/tda1997x.h>
40 MODULE_PARM_DESC(debug, "debug level (0-2)");
45 "HBR", /* High Bit Rate Audio */
[all …]
H A Dtw9910.c1 // SPDX-License-Identifier: GPL-2.0
13 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
26 #include <linux/v4l2-mediabus.h>
30 #include <media/v4l2-subdev.h>
45 #define CROP_HI 0x07 /* Cropping Register, High */
52 #define SCALE_HI 0x0E /* Scaling Register, High */
136 #define IFSEL_S 0x10 /* 01 : S-video decoding */
146 /* 1 : ITU-R-656 compatible data sequence format */
147 #define LEN 0x40 /* 0 : 8-bit YCrCb 4:2:2 output format */
148 /* 1 : 16-bit YCrCb 4:2:2 output format.*/
[all …]
H A Dks0127.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * for the Matrox Marvel G200,G400 and Rainbow Runner-G series
20 * V1.1 Gerard v.d. Horst Added some debugoutput, reset the video-standard
31 #include <media/v4l2-device.h>
234 table[KS_HSCLH] = 0x00; /* Horizontal Scaling Ratio High */ in init_reg_defaults()
236 table[KS_VSCLH] = 0x00; /* Vertical Scaling Ratio High */ in init_reg_defaults()
250 table[KS_UVOFFH] = 0x00; /* UV Offset Adjustment High */ in init_reg_defaults()
257 table[KS_POLCTL] = 0x41; /* Timing Signal Polarity Control */ in init_reg_defaults()
273 /* Command Register F, update -immediately- */ in init_reg_defaults()
274 /* (there might come no vsync)*/ in init_reg_defaults()
[all …]
/linux/drivers/media/i2c/adv748x/
H A Dadv748x-hdmi.c1 // SPDX-License-Identifier: GPL-2.0+
11 #include <media/v4l2-ctrls.h>
12 #include <media/v4l2-device.h>
13 #include <media/v4l2-dv-timings.h>
14 #include <media/v4l2-ioctl.h>
16 #include <uapi/linux/v4l2-dv-timings.h>
20 /* -----------------------------------------------------------------------------
29 /* V4L2_DV_BT_CEA_720X480I59_94 - 0.5 MHz */
95 fmt->code = MEDIA_BUS_FMT_RGB888_1X24; in adv748x_hdmi_fill_format()
96 fmt->field = hdmi->timings.bt.interlaced ? in adv748x_hdmi_fill_format()
[all …]
/linux/drivers/regulator/
H A Drtmv20-regulator.c1 // SPDX-License-Identifier: GPL-2.0+
75 gpiod_set_value(priv->enable_gpio, 1); in rtmv20_lsw_enable()
80 /* HW re-enable, disable cache only and sync regcache here */ in rtmv20_lsw_enable()
81 regcache_cache_only(priv->regmap, false); in rtmv20_lsw_enable()
82 ret = regcache_sync(priv->regmap); in rtmv20_lsw_enable()
99 regcache_cache_only(priv->regmap, true); in rtmv20_lsw_disable()
100 regcache_mark_dirty(priv->regmap); in rtmv20_lsw_disable()
102 gpiod_set_value(priv->enable_gpio, 0); in rtmv20_lsw_disable()
113 return -EINVAL; in rtmv20_lsw_set_current_limit()
118 sel = (max_uA - RTMV20_LSW_MINUA) / RTMV20_LSW_STEPUA; in rtmv20_lsw_set_current_limit()
[all …]
/linux/drivers/gpu/drm/meson/
H A Dmeson_venc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
25 * - CVBS Encoding via the ENCI encoder and VDAC digital to analog converter
26 * - TMDS/HDMI Encoding via ENCI_DIV and ENCP
27 * - Setup of more clock rates for HDMI modes
31 * - LCD Panel encoding via ENCL
32 * - TV Panel encoding via ENCT
39 * vd1---| |-| | | VENC /---------|----VDAC
40 * vd2---| VIU |-| VPP |-|-----ENCI/-ENCI_DVI-|-|
41 * osd1--| |-| | | \ | X--HDMI-TX
42 * osd2--|_____|-|_____| | |\-ENCP--ENCP_DVI-|-|
[all …]
/linux/drivers/gpu/drm/
H A Ddrm_modes.c2 * Copyright © 1997-2003 by The XFree86 Project, Inc.
4 * Copyright © 2007-2008 Intel Corporation
6 * Copyright 2005-2006 Luc Verhaegen
53 * drm_mode_debug_printmodeline - print a mode to dmesg
65 * drm_mode_create - create a new display mode
87 * drm_mode_destroy - remove a mode
103 * drm_mode_probed_add - add a mode to a connector's probed_mode list
114 WARN_ON(!mutex_is_locked(&connector->dev->mode_config.mutex)); in drm_mode_probed_add()
116 list_add_tail(&mode->head, &connector->probed_modes); in drm_mode_probed_add()
127 * - https://web.archive.org/web/20220406232708/http://www.kolumbus.fi/pami1/video/pal_ntsc.html
[all …]
/linux/drivers/gpu/drm/stm/
H A Dltdc.c1 // SPDX-License-Identifier: GPL-2.0
15 #include <linux/media-bus-format.h>
46 #define CRTC_MASK GENMASK(NB_CRTC - 1, 0)
61 #define LAY_OFS (ldev->caps.layer_ofs)
87 #define LTDC_L1C0R (ldev->caps.layer_regs[0]) /* L1 configuration 0 */
88 #define LTDC_L1C1R (ldev->caps.layer_regs[1]) /* L1 configuration 1 */
89 #define LTDC_L1RCR (ldev->caps.layer_regs[2]) /* L1 reload control */
90 #define LTDC_L1CR (ldev->caps.layer_regs[3]) /* L1 control register */
91 #define LTDC_L1WHPCR (ldev->caps.layer_regs[4]) /* L1 window horizontal position configuration */
92 #define LTDC_L1WVPCR (ldev->caps.layer_regs[5]) /* L1 window vertical position configuration */
[all …]
/linux/drivers/media/pci/tw5864/
H A Dtw5864-reg.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * TW5864 driver - registers description
8 /* According to TW5864_datasheet_0.6d.pdf, tw5864b1-ds.pdf */
10 /* Register Description - Direct Map Space */
11 /* 0x0000 ~ 0x1ffc - H264 Register Map */
76 * 0->3 4 VLC data buffer in DDR (1M each)
77 * 0->7 8 VLC data buffer in DDR (512k each)
147 /* DDR-DPR Burst Read Enable */
157 * 0 Single R/W Access (Host <-> DDR)
158 * 1 Burst R/W Access (Host <-> DPR)
[all …]
/linux/drivers/gpu/drm/omapdrm/dss/
H A Dhdmi5_core.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
28 void __iomem *base = core->base; in hdmi5_core_ddc_init()
51 /* Standard Mode SCL High counter */ in hdmi5_core_ddc_init()
65 /* Fast Mode SCL High Counter */ in hdmi5_core_ddc_init()
86 /* NACK_POL to high */ in hdmi5_core_ddc_init()
92 /* ARBITRATION_POL to high */ in hdmi5_core_ddc_init()
98 /* DONE_POL to high */ in hdmi5_core_ddc_init()
107 void __iomem *base = core->base; in hdmi5_core_ddc_uninit()
118 void __iomem *base = core->base; in hdmi5_core_ddc_read()
[all …]
/linux/drivers/gpu/drm/bridge/
H A Dchipone-icn6211.c1 // SPDX-License-Identifier: GPL-2.0+
18 #include <linux/media-bus-format.h>
53 #define VSYNC 0x28 macro
214 return ret == val_size ? 0 : -EINVAL; in chipone_dsi_read()
240 ret = regmap_read(icn->regmap, reg, &pval); in chipone_readb()
247 return regmap_write(icn->regmap, reg, val); in chipone_writeb()
254 unsigned int mode_clock = mode->clock * 1000; in chipone_configure_pll()
271 * P is pre-divider, register PLL_REF_DIV[3:0] is 1:n divider in chipone_configure_pll()
274 * S is post-divider, register PLL_REF_DIV[7:5] is 2^(n+1) divider in chipone_configure_pll()
276 * It seems the PLL input clock after applying P pre-divider have in chipone_configure_pll()
[all …]
/linux/drivers/media/usb/gspca/
H A Dsonixb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2009-2011 Jean-François Moine <http://moinejf.free.fr>
14 0x10 high nibble red gain low nibble blue gain
17 0x05 red gain 0-127
18 0x06 blue gain 0-127
19 0x07 green gain 0-127
21 0x08-0x0f i2c / 3wire registers
24 0x15 hsize (hsize = register-value * 16)
25 0x16 vsize (vsize = register-value * 16)
27 0x18 bit 7 enables compression, bit 4-5 set image down scaling:
[all …]

12