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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DSwiftErrorValueTracking.cpp37 auto VReg = MF->getRegInfo().createVirtualRegister(RC); in getOrCreateVReg() local
38 VRegDefMap[Key] = VReg; in getOrCreateVReg()
39 VRegUpwardsUse[Key] = VReg; in getOrCreateVReg()
40 return VReg; in getOrCreateVReg()
46 const Value *Val, Register VReg) { in setCurrentVReg() argument
47 VRegDefMap[std::make_pair(MBB, Val)] = VReg; in setCurrentVReg()
59 Register VReg = MF->getRegInfo().createVirtualRegister(RC); in getOrCreateVRegDefAt() local
60 VRegDefUses[Key] = VReg; in getOrCreateVRegDefAt()
61 setCurrentVReg(MBB, Val, VReg); in getOrCreateVRegDefAt()
62 return VReg; in getOrCreateVRegDefAt()
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H A DMIRVRegNamerUtils.cpp1 //===---------- MIRVRegNamerUtils.cpp - MIR VReg Renaming Utilities -------===//
19 UseStableNamerHash("mir-vreg-namer-use-stable-hash", cl::init(false),
21 cl::desc("Use Stable Hashing for MIR VReg Renaming"));
47 for (const auto &VReg : VRegs) { in getVRegRenameMap() local
48 const Register Reg = VReg.getReg(); in getVRegRenameMap()
49 VRM[Reg] = createVirtualRegisterWithLowerName(Reg, GetUniqueVRegName(VReg)); in getVRegRenameMap()
139 Register VRegRenamer::createVirtualRegister(Register VReg) { in createVirtualRegister() argument
140 assert(VReg.isVirtual() && "Expected Virtual Registers"); in createVirtualRegister()
141 std::string Name = getInstructionOpcodeHash(*MRI.getVRegDef(VReg)); in createVirtualRegister()
142 return createVirtualRegisterWithLowerName(VReg, Name); in createVirtualRegister()
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H A DMIRVRegNamerUtils.h2 //===------------ MIRVRegNamerUtils.h - MIR VReg Renaming Utilities -------===//
55 /// the instruction defining that vreg.
67 /// Perform replacing of registers based on the <old,new> vreg map.
70 /// createVirtualRegister - Given an existing vreg, create a named vreg to
73 Register createVirtualRegister(Register VReg);
75 /// Create a vreg with name and return it.
76 Register createVirtualRegisterWithLowerName(Register VReg, StringRef Name);
79 /// vreg definition based on the semantics of the instruction.
88 /// will be used as prefix for the vreg names.
H A DRegAllocPBQP.cpp158 /// Finds the initial set of vreg intervals to allocate.
164 /// Spill the given VReg.
165 void spillVReg(Register VReg, SmallVectorImpl<Register> &NewIntervals,
330 Register VReg = G.getNodeMetadata(NId).getVReg(); in apply() local
331 LiveInterval &LI = LIS.getInterval(VReg); in apply()
601 Register VReg = Worklist.back(); in initializeGraph() local
604 LiveInterval &VRegLI = LIS.getInterval(VReg); in initializeGraph()
614 const TargetRegisterClass *TRC = MRI.getRegClass(VReg); in initializeGraph()
620 // Compute an initial allowed set for the current vreg. in initializeGraph()
651 spillVReg(VReg, NewVRegs, MF, LIS, VRM, VRegSpiller); in initializeGraph()
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H A DLiveRangeEdit.cpp36 Register VReg = MRI.cloneVirtualRegister(OldReg); in createEmptyIntervalFrom() local
38 VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg)); in createEmptyIntervalFrom()
40 LiveInterval &LI = LIS.createEmptyInterval(VReg); in createEmptyIntervalFrom()
56 Register VReg = MRI.cloneVirtualRegister(OldReg); in createFrom() local
58 VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg)); in createFrom()
67 LIS.getInterval(VReg).markNotSpillable(); in createFrom()
68 return VReg; in createFrom()
450 Register VReg = LI->reg(); in eliminateDeadDefs() local
452 TheDelegate->LRE_WillShrinkVirtReg(VReg); in eliminateDeadDefs()
460 if (llvm::is_contained(RegsBeingSpilled, VReg)) in eliminateDeadDefs()
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H A DRegisterScavenging.cpp189 // Keep searching when we find a vreg since the spilled register will in findSurvivorBackwards()
190 // be usefull for this other vreg as well later. in findSurvivorBackwards()
333 /// Allocate a register for the virtual register \p VReg. The last use of
334 /// \p VReg is around the current position of the register scavenger \p RS.
339 Register VReg, bool ReserveAfter) { in scavengeVReg() argument
346 for (MachineOperand &MO : MRI.reg_nodbg_operands(VReg)) { in scavengeVReg()
353 if (!MI.readsRegister(VReg, &TRI)) { in scavengeVReg()
370 MRI.def_operands(VReg), [VReg, &TRI](const MachineOperand &MO) { in scavengeVReg()
371 return !MO.getParent()->readsRegister(VReg, &TRI); in scavengeVReg()
374 "Must have one definition that does not redefine vreg"); in scavengeVReg()
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/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyMachineFunctionInfo.h39 /// A mapping from CodeGen vreg index to WebAssembly register number.
42 /// A mapping from CodeGen vreg index to a boolean value indicating whether
59 // after it has been replaced by a vreg
98 assert(VarargVreg != -1U && "Vararg vreg hasn't been set"); in getVarargBufferVreg()
104 assert(BasePtrVreg != -1U && "Base ptr vreg hasn't been set"); in getBasePointerVreg()
109 assert(FrameBaseVreg != -1U && "Frame base vreg hasn't been set"); in getFrameBaseVreg()
122 void stackifyVReg(MachineRegisterInfo &MRI, Register VReg) { in stackifyVReg() argument
123 assert(MRI.getUniqueVRegDef(VReg)); in stackifyVReg()
124 auto I = VReg.virtRegIndex(); in stackifyVReg()
129 void unstackifyVReg(Register VReg) { in unstackifyVReg() argument
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H A DWebAssemblyRegNumbering.cpp75 LLVM_DEBUG(dbgs() << "Arg VReg " << printReg(MI.getOperand(0).getReg()) in runOnMachineFunction()
88 Register VReg = Register::index2VirtReg(VRegIdx); in runOnMachineFunction() local
90 if (MRI.use_empty(VReg)) in runOnMachineFunction()
93 if (MFI.isVRegStackified(VReg)) { in runOnMachineFunction()
94 LLVM_DEBUG(dbgs() << "VReg " << printReg(VReg) << " -> WAReg " in runOnMachineFunction()
96 MFI.setWAReg(VReg, INT32_MIN | NumStackRegs++); in runOnMachineFunction()
99 if (MFI.getWAReg(VReg) == WebAssembly::UnusedReg) { in runOnMachineFunction()
100 LLVM_DEBUG(dbgs() << "VReg " << printReg(VReg) << " -> WAReg " << CurReg in runOnMachineFunction()
102 MFI.setWAReg(VReg, CurReg++); in runOnMachineFunction()
H A DWebAssemblyReplacePhysRegs.cpp84 unsigned VReg = WebAssembly::NoRegister; in runOnMachineFunction() local
88 if (VReg == WebAssembly::NoRegister) { in runOnMachineFunction()
89 VReg = MRI.createVirtualRegister(RC); in runOnMachineFunction()
93 FI->setFrameBaseVreg(VReg); in runOnMachineFunction()
95 dbgs() << "replacing preg " << PReg << " with " << VReg << " (" in runOnMachineFunction()
96 << Register(VReg).virtRegIndex() << ")\n"; in runOnMachineFunction()
100 MO.setReg(VReg); in runOnMachineFunction()
/freebsd/lib/libc/arm/aeabi/
H A Daeabi_vfp.h55 #define LOAD_DREG(vreg, reg0, reg1) vmov vreg, reg1, reg0 argument
56 #define UNLOAD_DREG(reg0, reg1, vreg) vmov reg1, reg0, vreg argument
58 #define LOAD_DREG(vreg, reg0, reg1) vmov vreg, reg0, reg1 argument
59 #define UNLOAD_DREG(reg0, reg1, vreg) vmov reg0, reg1, vreg argument
63 #define LOAD_SREG(vreg, reg) vmov vreg, reg argument
64 #define UNLOAD_SREG(reg, vreg) vmov reg, vreg argument
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp98 // If the node is only used by a CopyToReg and the dest reg is a vreg, use in EmitCopyFromReg()
99 // the CopyToReg'd destination register instead of creating a new vreg. in EmitCopyFromReg()
201 // is a vreg in the same register class, use the CopyToReg'd destination in CreateVirtualRegisters()
202 // register instead of creating a new vreg. in CreateVirtualRegisters()
275 Register VReg = MRI->createVirtualRegister(RC); in getVR() local
277 TII->get(TargetOpcode::IMPLICIT_DEF), VReg); in getVR()
278 return VReg; in getVR()
325 Register VReg = getVR(Op, VRBaseMap); in AddRegisterOperand() local
333 // shrink VReg's register class within reason. For example, if VReg == GR32 in AddRegisterOperand()
334 // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP. in AddRegisterOperand()
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H A DSDNodeDbgValue.h38 VREG = 3 ///< Value is a virtual register. enumerator
66 /// Returns the Virtual Register for a VReg
68 assert(kind == VREG); in getVReg()
69 return u.VReg; in getVReg()
78 static SDDbgOperand fromVReg(Register VReg) { in fromVReg() argument
79 return SDDbgOperand(VReg.id(), VREG); in fromVReg()
94 case VREG:
111 unsigned VReg; ///< Valid for registers. member
123 assert((Kind == VREG || Kind == FRAMEIX) && in SDDbgOperand()
125 if (kind == VREG) in SDDbgOperand()
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/freebsd/contrib/byacc/test/btyacc/
H A Dcalc1.output9 6 | VREG '=' vexp '\n'
23 18 | VREG
40 VREG shift 3
71 line : VREG . '=' vexp '\n' (6)
72 vexp : VREG . (18)
93 VREG shift 14
109 VREG shift 14
183 line : VREG '=' . vexp '\n' (6)
186 VREG shift 14
203 vexp : VREG . (18)
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H A Dvarsyntax_calc1.output9 6 | VREG '=' vexp '\n'
23 18 | VREG
40 VREG shift 3
71 line : VREG . '=' vexp '\n' (6)
72 vexp : VREG . (18)
93 VREG shift 14
109 VREG shift 14
183 line : VREG '=' . vexp '\n' (6)
186 VREG shift 14
203 vexp : VREG . (18)
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H A Dbtyacc_calc1.output10 7 | VREG '=' vexp
23 18 | VREG
52 VREG shift 4
83 line : VREG . '=' vexp (7)
84 vexp : VREG . (18)
105 VREG shift 15
121 VREG shift 15
200 line : VREG '=' . vexp (7)
203 VREG shift 15
220 vexp : VREG . (18)
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/freebsd/contrib/byacc/test/yacc/
H A Dvarsyntax_calc1.output9 6 | VREG '=' vexp '\n'
23 18 | VREG
40 VREG shift 3
71 line : VREG . '=' vexp '\n' (6)
72 vexp : VREG . (18)
93 VREG shift 14
109 VREG shift 14
183 line : VREG '=' . vexp '\n' (6)
186 VREG shift 14
203 vexp : VREG . (18)
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H A Dcalc1.output9 6 | VREG '=' vexp '\n'
23 18 | VREG
40 VREG shift 3
71 line : VREG . '=' vexp '\n' (6)
72 vexp : VREG . (18)
93 VREG shift 14
109 VREG shift 14
183 line : VREG '=' . vexp '\n' (6)
186 VREG shift 14
203 vexp : VREG . (18)
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/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVGlobalRegistry.h33 // Initialized upon VReg definition in IRTranslator.
279 // and map it to the given VReg by creating an ASSIGN_TYPE instruction.
280 SPIRVType *assignTypeToVReg(const Type *Type, Register VReg,
284 SPIRVType *assignIntTypeToVReg(unsigned BitWidth, Register VReg,
286 SPIRVType *assignFloatTypeToVReg(unsigned BitWidth, Register VReg,
289 Register VReg, MachineInstr &I,
293 // used to map it to the given VReg via an ASSIGN_TYPE instruction.
294 void assignSPIRVTypeToVReg(SPIRVType *Type, Register VReg,
336 // Return the SPIR-V type instruction corresponding to the given VReg, or
341 SPIRVType *getSPIRVTypeForVReg(Register VReg,
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineRegisterInfo.h51 /// registers, including vreg register classes, use/def chains for registers,
77 /// Each element in this list contains the register class of the vreg and the
83 /// Map for recovering vreg name from vreg number.
87 /// StringSet that is used to unique vreg names.
225 bool shouldTrackSubRegLiveness(Register VReg) const { in shouldTrackSubRegLiveness() argument
226 assert(VReg.isVirtual() && "Must pass a VReg"); in shouldTrackSubRegLiveness()
227 const TargetRegisterClass *RC = getRegClassOrNull(VReg); in shouldTrackSubRegLiveness()
764 LLVM_ABI Register cloneVirtualRegister(Register VReg, StringRef Name = "");
774 /// Set the low-level type of \p VReg to \p Ty.
775 LLVM_ABI void setType(Register VReg, LLT Ty);
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/freebsd/contrib/byacc/test/
H A Dvarsyntax_calc1.y26 INTERVAL vreg[26]; variable
34 int ival; // dreg & vreg array index values
39 %token <ival> DREG VREG // indices into dreg, vreg arrays */
70 | VREG '=' vexp '\n'
72 vreg[$1] = $3;
125 | VREG
127 $$ = vreg[$1];
202 return (VREG);
H A Dbtyacc_calc1.y23 INTERVAL vreg[26]; variable
36 %token <ival> DREG VREG /* indices into dreg, vreg arrays */
70 | VREG '=' vexp
72 vreg[$1] = $3;
121 | VREG
123 $$ = vreg[$1];
211 return (VREG); in YYLEX_DECL()
H A Dcalc1.y25 INTERVAL vreg[26]; variable
38 %token <ival> DREG VREG /* indices into dreg, vreg arrays */
68 | VREG '=' vexp '\n'
70 vreg[$1] = $3;
123 | VREG
125 $$ = vreg[$1];
200 return (VREG); in yylex()
/freebsd/share/doc/psd/15.yacc/
H A Dssc155 INTERVAL vreg[ 26 ];
167 %token <ival> DREG VREG /* indices into dreg, vreg arrays */
193 | VREG \'=\' vexp \'\en\'
194 { vreg[$1] = $3; }
227 | VREG
228 { $$ = vreg[$1]; }
270 return( VREG );
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoVPseudos.td169 class LMULInfo<int lmul, int oct, VReg regclass, VReg wregclass,
170 VReg f2regclass, VReg f4regclass, VReg f8regclass, string mx> {
172 VReg vrclass = regclass;
173 VReg wvrclass = wregclass;
174 VReg f8vrclass = f8regclass;
175 VReg f4vrclass = f4regclass;
176 VReg f2vrclass = f2regclass;
275 VReg RC = !cast<VReg>("VRN" # nf # !cond(!eq(m.value, V_MF8.value): V_M1.MX,
291 VReg RegClass = M.vrclass;
748 class GetVRegNoV0<VReg VRegClass> {
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPURewriteAGPRCopyMFMA.cpp105 Register VReg = Register::index2VirtReg(I); in run() local
106 Register PhysReg = VRM.getPhys(VReg); in run()
111 const TargetRegisterClass *VirtRegRC = MRI.getRegClass(VReg); in run()
119 LiveInterval &LI = LIS.getInterval(VReg); in run()
154 << " Dst=[" << printReg(VReg) << " => " in run()
205 MRI.setRegClass(VReg, AssignedRC); in run()
211 MRI.replaceRegWith(CopySrcReg, VReg); in run()
225 LIS.removeInterval(VReg); in run()
226 LIS.createAndComputeVirtRegInterval(VReg); in run()

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