Searched +full:vrange +full:- +full:high +full:- +full:enable (Results 1 – 4 of 4) sorted by relevance
| /freebsd/sys/contrib/device-tree/Bindings/hwmon/ |
| H A D | adi,adm1177.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Michael Hennerich <michael.hennerich@analog.com> 14 https://www.analog.com/media/en/technical-documentation/data-sheets/ADM1177.pdf 19 - adi,adm1177 24 avcc-supply: 28 shunt-resistor-micro-ohms: 33 adi,shutdown-threshold-microamp: 37 based on shunt-resistor-micro-ohms. [all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ScheduleZnver4.td | 1 //=- X86ScheduleZnver4.td - X86 Znver4 Scheduling ------------*- tablegen -*-=// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 14 //===----------------------------------------------------------------------===// 23 // outstanding operations (integer, load/store, and floating-point) and is 26 // to 320 macro ops in-flight in non-SMT mode or 160 per thread in SMT mode. 30 // At each set-way intersection is an entry containing up to 8 macro ops. 33 // the op-cache, we limit the loop buffer to 9*12 = 108 to avoid loop 34 // unrolling leading to excessive filling of the op-cache from frontend. 37 // The L1 data cache has a 4- or 5- cycle integer load-to-use latency. [all …]
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| H A D | X86ISelLowering.h | 1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 12 //===----------------------------------------------------------------------===// 62 /// #0 - The incoming token chain 63 /// #1 - The callee 64 /// #2 - The number of arg bytes the caller pushes on the stack. 65 /// #3 - The number of arg bytes the callee pops off the stack. 66 /// #4 - The value to pass in AL/AX/EAX (optional) 67 /// #5 - The value to pass in DL/DX/EDX (optional) [all …]
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| H A D | X86ISelLowering.cpp | 1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 12 //===----------------------------------------------------------------------===// 71 #define DEBUG_TYPE "x86-isel" 74 "x86-experimental-pref-innermost-loop-alignment", cl::init(4), 78 "alignment set by x86-experimental-pref-loop-alignment."), 82 "x86-br-merging-base-cost", cl::init(2), 88 "will be merged, and above which conditionals will be split. Set to -1 " 93 "x86-br-merging-ccmp-bias", cl::init(6), [all …]
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