| /linux/drivers/remoteproc/ |
| H A D | ingenic_rproc.c | 53 * struct vpu - Ingenic VPU remoteproc private structure
55 * @clks: pointers to the VPU and AUX clocks
61 struct vpu { struct
71 struct vpu *vpu = rproc->priv; in ingenic_rproc_prepare() local
75 ret = clk_bulk_prepare_enable(ARRAY_SIZE(vpu->clks), vpu->clks); in ingenic_rproc_prepare()
77 dev_err(vpu->dev, "Unable to start clocks: %d\n", ret); in ingenic_rproc_prepare()
84 struct vpu *vpu = rproc->priv; in ingenic_rproc_unprepare() local
86 clk_bulk_disable_unprepare(ARRAY_SIZE(vpu->clks), vpu->clks); in ingenic_rproc_unprepare()
93 struct vpu *vpu = rproc->priv; in ingenic_rproc_start() local
96 enable_irq(vpu->irq); in ingenic_rproc_start()
[all …]
|
| /linux/drivers/media/platform/verisilicon/ |
| H A D | hantro_drv.c | 3 * Hantro VPU codec driver
32 #define DRIVER_NAME "hantro-vpu"
62 static void hantro_job_finish_no_pm(struct hantro_dev *vpu, in hantro_job_finish_no_pm() argument
89 static void hantro_job_finish(struct hantro_dev *vpu, in hantro_job_finish() argument
93 pm_runtime_put_autosuspend(vpu->dev); in hantro_job_finish()
95 clk_bulk_disable(vpu->variant->num_clocks, vpu->clocks); in hantro_job_finish()
97 hantro_job_finish_no_pm(vpu, ctx, result); in hantro_job_finish()
100 void hantro_irq_done(struct hantro_dev *vpu, in hantro_irq_done() argument
104 v4l2_m2m_get_curr_priv(vpu->m2m_dev); in hantro_irq_done()
111 if (cancel_delayed_work(&vpu->watchdog_work)) { in hantro_irq_done()
[all …]
|
| H A D | rockchip_vpu2_hw_jpeg_enc.c | 3 * Hantro VPU codec driver
9 * The VPU JPEG encoder produces JPEG baseline sequential format.
35 static void rockchip_vpu2_set_src_img_ctrl(struct hantro_dev *vpu, in rockchip_vpu2_set_src_img_ctrl() argument
51 vepu_write_relaxed(vpu, reg, VEPU_REG_INPUT_LUMA_INFO); in rockchip_vpu2_set_src_img_ctrl()
61 vepu_write_relaxed(vpu, reg, VEPU_REG_ENC_OVER_FILL_STRM_OFFSET); in rockchip_vpu2_set_src_img_ctrl()
64 vepu_write_relaxed(vpu, reg, VEPU_REG_ENC_CTRL1); in rockchip_vpu2_set_src_img_ctrl()
67 static void rockchip_vpu2_jpeg_enc_set_buffers(struct hantro_dev *vpu, in rockchip_vpu2_jpeg_enc_set_buffers() argument
82 vepu_write_relaxed(vpu, vb2_dma_contig_plane_dma_addr(dst_buf, 0) + in rockchip_vpu2_jpeg_enc_set_buffers()
85 vepu_write_relaxed(vpu, size_left, VEPU_REG_STR_BUF_LIMIT); in rockchip_vpu2_jpeg_enc_set_buffers()
89 vepu_write_relaxed(vpu, src[0], VEPU_REG_ADDR_IN_PLANE_0); in rockchip_vpu2_jpeg_enc_set_buffers()
[all …]
|
| H A D | hantro_h1_jpeg_enc.c | 3 * Hantro VPU codec driver
18 static void hantro_h1_set_src_img_ctrl(struct hantro_dev *vpu, in hantro_h1_set_src_img_ctrl() argument
37 vepu_write_relaxed(vpu, reg, H1_REG_IN_IMG_CTRL); in hantro_h1_set_src_img_ctrl()
40 static void hantro_h1_jpeg_enc_set_buffers(struct hantro_dev *vpu, in hantro_h1_jpeg_enc_set_buffers() argument
55 vepu_write_relaxed(vpu, vb2_dma_contig_plane_dma_addr(dst_buf, 0) + in hantro_h1_jpeg_enc_set_buffers()
58 vepu_write_relaxed(vpu, size_left, H1_REG_STR_BUF_LIMIT); in hantro_h1_jpeg_enc_set_buffers()
63 vepu_write_relaxed(vpu, src[0], H1_REG_ADDR_IN_PLANE_0); in hantro_h1_jpeg_enc_set_buffers()
67 vepu_write_relaxed(vpu, src[0], H1_REG_ADDR_IN_PLANE_0); in hantro_h1_jpeg_enc_set_buffers()
68 vepu_write_relaxed(vpu, src[1], H1_REG_ADDR_IN_PLANE_1); in hantro_h1_jpeg_enc_set_buffers()
73 vepu_write_relaxed(vpu, src[0], H1_REG_ADDR_IN_PLANE_0); in hantro_h1_jpeg_enc_set_buffers()
[all …]
|
| H A D | rockchip_vpu2_hw_vp8_dec.c | 3 * Rockchip VPU codec vp8 decode driver
280 struct hantro_dev *vpu = ctx->dev; in cfg_lf() local
285 hantro_reg_write(vpu, &vp8_dec_lf_level[0], lf->level); in cfg_lf()
291 hantro_reg_write(vpu, &vp8_dec_lf_level[i], lf_level); in cfg_lf()
295 hantro_reg_write(vpu, &vp8_dec_lf_level[i], in cfg_lf()
302 vdpu_write_relaxed(vpu, reg, VDPU_REG_FILTER_MB_ADJ); in cfg_lf()
306 hantro_reg_write(vpu, &vp8_dec_mb_adj[i], in cfg_lf()
308 hantro_reg_write(vpu, &vp8_dec_ref_adj[i], in cfg_lf()
319 struct hantro_dev *vpu = ctx->dev; in cfg_qp() local
323 hantro_reg_write(vpu, &vp8_dec_quant[0], q->y_ac_qi); in cfg_qp()
[all …]
|
| H A D | hantro_g1_h264_dec.c | 3 * Rockchip RK3288 VPU codec driver
28 struct hantro_dev *vpu = ctx->dev; in set_params() local
49 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL0); in set_params()
55 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL1); in set_params()
65 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL2); in set_params()
71 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL3); in set_params()
85 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL4); in set_params()
100 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL5); in set_params()
107 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL6); in set_params()
110 vdpu_write_relaxed(vpu, 0, G1_REG_ERR_CONC); in set_params()
[all …]
|
| H A D | rockchip_vpu2_hw_mpeg2_dec.c | 3 * Hantro VPU codec driver
83 rockchip_vpu2_mpeg2_dec_set_quantisation(struct hantro_dev *vpu, in rockchip_vpu2_mpeg2_dec_set_quantisation() argument
90 vdpu_write_relaxed(vpu, ctx->mpeg2_dec.qtable.dma, VDPU_REG_QTABLE_BASE); in rockchip_vpu2_mpeg2_dec_set_quantisation()
94 rockchip_vpu2_mpeg2_dec_set_buffers(struct hantro_dev *vpu, in rockchip_vpu2_mpeg2_dec_set_buffers() argument
114 vdpu_write_relaxed(vpu, addr, VDPU_REG_RLC_VLC_BASE); in rockchip_vpu2_mpeg2_dec_set_buffers()
122 vdpu_write_relaxed(vpu, addr, VDPU_REG_DEC_OUT_BASE); in rockchip_vpu2_mpeg2_dec_set_buffers()
136 vdpu_write_relaxed(vpu, forward_addr, VDPU_REG_REFER0_BASE); in rockchip_vpu2_mpeg2_dec_set_buffers()
137 vdpu_write_relaxed(vpu, forward_addr, VDPU_REG_REFER1_BASE); in rockchip_vpu2_mpeg2_dec_set_buffers()
139 vdpu_write_relaxed(vpu, forward_addr, VDPU_REG_REFER0_BASE); in rockchip_vpu2_mpeg2_dec_set_buffers()
140 vdpu_write_relaxed(vpu, current_addr, VDPU_REG_REFER1_BASE); in rockchip_vpu2_mpeg2_dec_set_buffers()
[all …]
|
| H A D | hantro_g1_vp8_dec.c | 139 struct hantro_dev *vpu = ctx->dev; in cfg_lf() local
144 hantro_reg_write(vpu, &vp8_dec_lf_level[0], lf->level); in cfg_lf()
150 hantro_reg_write(vpu, &vp8_dec_lf_level[i], lf_level); in cfg_lf()
154 hantro_reg_write(vpu, &vp8_dec_lf_level[i], in cfg_lf()
161 vdpu_write_relaxed(vpu, reg, G1_REG_REF_PIC(0)); in cfg_lf()
165 hantro_reg_write(vpu, &vp8_dec_mb_adj[i], in cfg_lf()
167 hantro_reg_write(vpu, &vp8_dec_ref_adj[i], in cfg_lf()
181 struct hantro_dev *vpu = ctx->dev; in cfg_qp() local
185 hantro_reg_write(vpu, &vp8_dec_quant[0], q->y_ac_qi); in cfg_qp()
191 hantro_reg_write(vpu, &vp8_dec_quant[i], quant); in cfg_qp()
[all …]
|
| H A D | hantro_g1_mpeg2_dec.c | 3 * Hantro VPU codec driver
81 hantro_g1_mpeg2_dec_set_quantisation(struct hantro_dev *vpu, in hantro_g1_mpeg2_dec_set_quantisation() argument
88 vdpu_write_relaxed(vpu, ctx->mpeg2_dec.qtable.dma, G1_REG_QTABLE_BASE); in hantro_g1_mpeg2_dec_set_quantisation()
92 hantro_g1_mpeg2_dec_set_buffers(struct hantro_dev *vpu, struct hantro_ctx *ctx, in hantro_g1_mpeg2_dec_set_buffers() argument
111 vdpu_write_relaxed(vpu, addr, G1_REG_RLC_VLC_BASE); in hantro_g1_mpeg2_dec_set_buffers()
119 vdpu_write_relaxed(vpu, addr, G1_REG_DEC_OUT_BASE); in hantro_g1_mpeg2_dec_set_buffers()
133 vdpu_write_relaxed(vpu, forward_addr, G1_REG_REFER0_BASE); in hantro_g1_mpeg2_dec_set_buffers()
134 vdpu_write_relaxed(vpu, forward_addr, G1_REG_REFER1_BASE); in hantro_g1_mpeg2_dec_set_buffers()
136 vdpu_write_relaxed(vpu, forward_addr, G1_REG_REFER0_BASE); in hantro_g1_mpeg2_dec_set_buffers()
137 vdpu_write_relaxed(vpu, current_addr, G1_REG_REFER1_BASE); in hantro_g1_mpeg2_dec_set_buffers()
[all …]
|
| H A D | hantro_g1.c | 3 * Hantro VPU codec driver
16 struct hantro_dev *vpu = dev_id; in hantro_g1_irq() local
20 status = vdpu_read(vpu, G1_REG_INTERRUPT); in hantro_g1_irq()
24 vdpu_write(vpu, 0, G1_REG_INTERRUPT); in hantro_g1_irq()
25 vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG); in hantro_g1_irq()
27 hantro_irq_done(vpu, state); in hantro_g1_irq()
34 struct hantro_dev *vpu = ctx->dev; in hantro_g1_reset() local
36 vdpu_write(vpu, G1_REG_INTERRUPT_DEC_IRQ_DIS, G1_REG_INTERRUPT); in hantro_g1_reset()
37 vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG); in hantro_g1_reset()
38 vdpu_write(vpu, 1, G1_REG_SOFT_RESET); in hantro_g1_reset()
|
| H A D | rockchip_vpu2_hw_h264_dec.c | 3 * Hantro VPU codec driver
199 struct hantro_dev *vpu = ctx->dev; in set_params() local
207 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(50)); in set_params()
211 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(51)); in set_params()
216 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(52)); in set_params()
219 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(53)); in set_params()
227 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(54)); in set_params()
233 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(56)); in set_params()
248 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(57)); in set_params()
253 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(59)); in set_params()
[all …]
|
| H A D | hantro_hevc.c | 3 * Hantro VPU HEVC codec driver
77 struct hantro_dev *vpu = ctx->dev; in tile_buffer_reallocate() local
92 dma_free_coherent(vpu->dev, hevc_dec->tile_filter.size, in tile_buffer_reallocate()
99 dma_free_coherent(vpu->dev, hevc_dec->tile_sao.size, in tile_buffer_reallocate()
106 dma_free_coherent(vpu->dev, hevc_dec->tile_bsd.size, in tile_buffer_reallocate()
113 hevc_dec->tile_filter.cpu = dma_alloc_coherent(vpu->dev, size, in tile_buffer_reallocate()
121 hevc_dec->tile_sao.cpu = dma_alloc_coherent(vpu->dev, size, in tile_buffer_reallocate()
129 hevc_dec->tile_bsd.cpu = dma_alloc_coherent(vpu->dev, size, in tile_buffer_reallocate()
142 dma_free_coherent(vpu->dev, hevc_dec->tile_sao.size, in tile_buffer_reallocate()
149 dma_free_coherent(vpu->dev, hevc_dec->tile_filter.size, in tile_buffer_reallocate()
[all …]
|
| /linux/drivers/media/platform/mediatek/mdp/ |
| H A D | mtk_mdp_vpu.c | 13 static inline struct mtk_mdp_ctx *vpu_to_ctx(struct mtk_mdp_vpu *vpu) in vpu_to_ctx() argument
15 return container_of(vpu, struct mtk_mdp_ctx, vpu); in vpu_to_ctx()
20 struct mtk_mdp_vpu *vpu = (struct mtk_mdp_vpu *) in mtk_mdp_vpu_handle_init_ack() local
23 /* mapping VPU address to kernel virtual address */ in mtk_mdp_vpu_handle_init_ack()
24 vpu->vsi = (struct mdp_process_vsi *) in mtk_mdp_vpu_handle_init_ack()
25 vpu_mapping_dm_addr(vpu->pdev, msg->vpu_inst_addr); in mtk_mdp_vpu_handle_init_ack()
26 vpu->inst_addr = msg->vpu_inst_addr; in mtk_mdp_vpu_handle_init_ack()
34 struct mtk_mdp_vpu *vpu = (struct mtk_mdp_vpu *) in mtk_mdp_vpu_ipi_handler() local
38 vpu->failure = msg->status; in mtk_mdp_vpu_ipi_handler()
39 if (!vpu->failure) { in mtk_mdp_vpu_ipi_handler()
[all …]
|
| H A D | mtk_mdp_vpu.h | 15 * struct mtk_mdp_vpu - VPU instance for MDP
16 * @pdev : pointer to the VPU platform device
17 * @inst_addr : VPU MDP instance address
18 * @failure : VPU execution result status
19 * @vsi : VPU shared information
29 int mtk_mdp_vpu_init(struct mtk_mdp_vpu *vpu);
30 int mtk_mdp_vpu_deinit(struct mtk_mdp_vpu *vpu);
31 int mtk_mdp_vpu_process(struct mtk_mdp_vpu *vpu);
|
| /linux/drivers/media/platform/mediatek/vcodec/decoder/ |
| H A D | vdec_vpu_if.h | 13 * struct vdec_vpu_inst - VPU instance for video codec
16 * @vsi : driver structure allocated by VPU side and shared to AP side
18 * @failure : VPU execution result status, 0: success, others: fail
19 * @inst_addr : VPU decoder instance address
23 * @signaled : 1 - Host has received ack message from VPU, 0 - not received
25 * @wq : wait queue to wait VPU message ack
49 * vpu_dec_init - init decoder instance and allocate required resource in VPU.
51 * @vpu: instance for vdec_vpu_inst
53 int vpu_dec_init(struct vdec_vpu_inst *vpu);
59 * @vpu : instance for vdec_vpu_inst
[all …]
|
| H A D | vdec_ipi_msg.h | 11 * enum vdec_ipi_msgid - message id between AP and VPU
12 * @AP_IPIMSG_XXX : AP to VPU cmd message id
13 * @VPU_IPIMSG_XXX_ACK : VPU ack AP cmd message id
36 * struct vdec_ap_ipi_cmd - generic AP to VPU ipi command format
38 * @vpu_inst_addr : VPU decoder instance address. Used if ABI version < 2.
54 * struct vdec_vpu_ipi_ack - generic VPU to AP ipi command format
56 * @status : VPU exeuction result
80 * @vpu_inst_addr : VPU decoder instance address. Used if ABI version < 2.
101 * @status : VPU exeuction result
103 * @vpu_inst_addr : VPU decoder instance address
[all …]
|
| /linux/drivers/media/platform/mediatek/vcodec/encoder/ |
| H A D | venc_ipi_msg.h | 16 * enum venc_ipi_msg_id - message id between AP and VPU
18 * @AP_IPIMSG_ENC_XXX: AP to VPU cmd message id
19 * @VPU_IPIMSG_ENC_XXX_DONE: VPU ack AP cmd message id
34 * struct venc_ap_ipi_msg_init - AP to VPU init cmd structure
36 * @reserved: reserved for future use. vpu is running in 32bit. Without
38 * will be different between kernel and vpu
49 * struct venc_ap_ipi_msg_set_param - AP to VPU set_param cmd structure
51 * @vpu_inst_addr: VPU encoder instance addr
71 * struct venc_ap_ipi_msg_enc - AP to VPU enc cmd structure
73 * @vpu_inst_addr: VPU encoder instance addr
[all …]
|
| H A D | venc_vpu_if.h | 13 * struct venc_vpu_inst - encoder VPU driver instance
14 * @wq_hd: wait queue used for vpu cmd trigger then wait vpu interrupt done
15 * @signaled: flag used for checking vpu interrupt done
16 * @failure: flag to show vpu cmd succeeds or not
20 * @inst_addr: VPU instance addr
21 * @vsi: driver structure allocated by VPU side and shared to AP side for
40 int vpu_enc_init(struct venc_vpu_inst *vpu);
41 int vpu_enc_set_param(struct venc_vpu_inst *vpu,
44 int vpu_enc_encode(struct venc_vpu_inst *vpu, unsigned int bs_mode,
48 int vpu_enc_deinit(struct venc_vpu_inst *vpu);
|
| /linux/drivers/media/platform/amphion/ |
| H A D | vpu_imx8q.c | 15 #include "vpu.h"
42 int vpu_imx8q_setup_dec(struct vpu_dev *vpu) in vpu_imx8q_setup_dec() argument
46 vpu_writel(vpu, offset + MFD_BLK_CTRL_MFD_SYS_CLOCK_ENABLE_SET, 0x1f); in vpu_imx8q_setup_dec()
47 vpu_writel(vpu, offset + MFD_BLK_CTRL_MFD_SYS_RESET_SET, 0xffffffff); in vpu_imx8q_setup_dec()
52 int vpu_imx8q_setup_enc(struct vpu_dev *vpu) in vpu_imx8q_setup_enc() argument
57 int vpu_imx8q_setup(struct vpu_dev *vpu) in vpu_imx8q_setup() argument
61 vpu_readl(vpu, offset + 0x108); in vpu_imx8q_setup()
63 vpu_writel(vpu, offset + SCB_BLK_CTRL_SCB_CLK_ENABLE_SET, 0x1); in vpu_imx8q_setup()
64 vpu_writel(vpu, offset + 0x190, 0xffffffff); in vpu_imx8q_setup()
65 vpu_writel(vpu, offset + SCB_BLK_CTRL_XMEM_RESET_SET, 0xffffffff); in vpu_imx8q_setup()
[all …]
|
| /linux/drivers/accel/ivpu/ |
| H A D | vpu_boot_api.h | 109 /** VPU scheduling mode. By default, OS scheduling is used. */
119 /** VPU MCA ECC signalling mode. By default, no signalling is used */
131 * defines the list of logging destinations supported by the VPU firmware (NOTE:
132 * a specific VPU FW binary may support only a subset of such output
169 /* VPU 30xx HW component IDs are sequential, so define first and last IDs. */
188 * It will be used by VPU to swap between normal and focus priorities
240 * ShaveNN FW section VPU base address
249 /* ARM -> VPU doorbell interrupt. ARM is notifying VPU of async command or compute job. */
251 /* VPU -> ARM job done interrupt. VPU is notifying ARM of compute job completion. */
253 /* VPU -> ARM IRQ line to use to request MMU update. */
[all …]
|
| /linux/drivers/media/platform/mediatek/vcodec/decoder/vdec/ |
| H A D | vdec_h264_if.c | 90 * between VPU and Host.
91 * The memory is allocated by VPU then mapping to Host
93 * by VPU.
95 * VPU-W/R: VPU is write/reader on this item
96 * @hdr_buf : Header parsing buffer (AP-W, VPU-R)
97 * @pred_buf_dma : HW working prediction buffer dma address (AP-W, VPU-R)
98 * @mv_buf_dma : HW working motion vector buffer dma address (AP-W, VPU-R)
99 * @list_free : free frame buffer ring list (AP-W/R, VPU-W)
100 * @list_disp : display frame buffer ring list (AP-R, VPU-W)
101 * @dec : decode information (AP-R, VPU-W)
[all …]
|
| H A D | vdec_h264_req_if.c | 51 * between VPU and Host.
52 * The memory is allocated by VPU then mapping to Host
54 * by VPU.
56 * VPU-W/R: VPU is write/reader on this item
57 * @pred_buf_dma : HW working prediction buffer dma address (AP-W, VPU-R)
58 * @mv_buf_dma : HW working motion vector buffer dma address (AP-W, VPU-R)
59 * @dec : decode information (AP-R, VPU-W)
60 * @pic : picture information (AP-R, VPU-W)
61 * @crop : crop information (AP-R, VPU-W)
79 * @vpu : VPU instance
[all …]
|
| H A D | vdec_vp8_req_if.c | 74 * struct vdec_vp8_slice_vsi - VPU shared information
94 * @vpu: VPU instance for decoder
95 * @vsi: VPU share information
103 struct vdec_vpu_inst vpu; member
125 vpu_dec_get_param(&inst->vpu, data, 3, GET_PARAM_PIC_INFO); in vdec_vp8_slice_get_pic_info()
129 ctx->picinfo.fb_sz[0] = inst->vpu.fb_sz[0]; in vdec_vp8_slice_get_pic_info()
130 ctx->picinfo.fb_sz[1] = inst->vpu.fb_sz[1]; in vdec_vp8_slice_get_pic_info()
284 inst->vpu.id = SCP_IPI_VDEC_LAT; in vdec_vp8_slice_init()
285 inst->vpu.core_id = SCP_IPI_VDEC_CORE; in vdec_vp8_slice_init()
286 inst->vpu.ctx = ctx; in vdec_vp8_slice_init()
[all …]
|
| /linux/drivers/media/platform/mediatek/vcodec/encoder/venc/ |
| H A D | venc_vp8_if.c | 49 * VPU-W/R: VPU is write/reader on this item
79 * VPU-W/R: VPU is write/reader on this item
81 * @vpua: VPU side memory addr which is used by RC_CODE
91 * struct venc_vp8_vsi - Structure for VPU driver control and info share
93 * VPU-W/R: VPU is write/reader on this item
94 * This structure is allocated in VPU side and shared to AP side.
96 * @work_bufs: working buffer information in VPU side
102 * register setting in VPU side.
118 * @vpu_inst: VPU instance to exchange information between AP and VPU
119 * @vsi: driver structure allocated by VPU side and shared to AP side for
[all …]
|
| H A D | venc_h264_if.c | 64 * VPU-W/R: VPU is write/reader on this item
99 * VPU-W/R: VPU is write/reader on this item
101 * @vpua: VPU side memory addr which is used by RC_CODE
111 * struct venc_h264_vsi - Structure for VPU driver control and info share
113 * VPU-W/R: VPU is write/reader on this item
114 * This structure is allocated in VPU side and shared to AP side.
116 * @work_bufs: working buffer information in VPU side
122 * register setting in VPU side.
132 * VPU-W/R: VPU is write/reader on this item
173 * VPU-W/R: VPU is write/reader on this item
[all …]
|