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/freebsd/sys/contrib/device-tree/src/arm64/rockchip/
H A Drk3568-radxa-e25.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
4 #include "rk3568-radxa-cm3i.dtsi"
14 pwm-leds {
15 compatible = "pwm-leds-multicolor";
17 multi-le
[all...]
H A Drk3568-nanopi-r5c.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
9 /dts-v1/;
10 #include "rk3568-nanopi-r5s.dtsi"
14 compatible = "friendlyarm,nanopi-r5c", "rockchip,rk3568";
16 gpio-keys {
17 compatible = "gpio-keys";
18 pinctrl-names = "default";
19 pinctrl-0 = <&reset_button_pin>;
21 button-reset {
22 debounce-interval = <50>;
[all …]
H A Drk3568-nanopi-r5s.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
9 /dts-v1/;
10 #include "rk3568-nanopi-r5s.dtsi"
14 compatible = "friendlyarm,nanopi-r5s", "rockchip,rk3568";
20 gpio-leds {
21 compatible = "gpio-leds";
22 pinctrl-names = "default";
23 pinctrl-0 = <&lan1_led_pin>, <&lan2_led_pin>, <&power_led_pin>, <&wan_led_pin>;
25 led-lan1 {
28 function-enumerator = <1>;
[all …]
H A Drk3568-fastrhino-r66s.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 /dts-v1/;
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/leds/common.h>
7 #include <dt-bindings/pinctrl/rockchip.h>
8 #include <dt-bindings/soc/rockchip,vop2.h>
13 stdout-path = "serial2:1500000n8";
16 gpio-keys {
17 compatible = "gpio-keys";
[all …]
H A Drk3399-roc-pc-mezzanine.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd
7 /dts-v1/;
8 #include "rk3399-roc-pc.dtsi"
11 model = "Firefly ROC-RK3399-PC Mezzanine Board";
12 compatible = "firefly,roc-rk3399-pc-mezzanine", "rockchip,rk3399";
19 poe_12v: poe-12v {
20 compatible = "regulator-fixed";
21 regulator-name = "poe_12v";
22 regulator-always-on;
[all …]
H A Drk3399-nanopc-t4.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * FriendlyElec NanoPC-T4 board device tree source
11 /dts-v1/;
12 #include "rk3399-nanopi4.dtsi"
15 model = "FriendlyElec NanoPC-T4";
16 compatible = "friendlyarm,nanopc-t4", "rockchip,rk3399";
18 vcc12v0_sys: vcc12v0-sys {
19 compatible = "regulator-fixed";
20 regulator-always-on;
21 regulator-boot-on;
[all …]
H A Drk3399-nanopi-r4s.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * FriendlyElec NanoPC-T4 board device tree source
15 /dts-v1/;
16 #include "rk3399-nanopi4.dtsi"
20 compatible = "friendlyarm,nanopi-r4s", "rockchip,rk3399";
22 /delete-node/ display-subsystem;
24 gpio-leds {
25 pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>;
27 /delete-node/ led-0;
29 lan_led: led-lan {
[all …]
H A Drk3566-soquartz-blade.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/leds/common.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
10 #include "rk3566-soquartz.dtsi"
14 compatible = "pine64,soquartz-blad
[all...]
H A Drk3566-soquartz-cm4.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
5 #include "rk3566-soquartz.dtsi"
8 model = "Pine64 RK3566 SoQuartz with CM4-IO Carrier Board";
9 compatible = "pine64,soquartz-cm4io", "pine64,soquartz", "rockchip,rk3566";
16 vcc12v_dcin: vcc12v-dcin-regulator {
17 compatible = "regulator-fixe
[all...]
H A Drk3566-soquartz-model-a.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
5 #include "rk3566-soquartz.dtsi"
9 compatible = "pine64,soquartz-model-a", "pine64,soquartz", "rockchip,rk3566";
16 vcc12v_dcin: vcc12v-dcin-regulator {
17 compatible = "regulator-fixe
[all...]
H A Drk3568-lubancat-2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/soc/rockchip,vop2.h>
17 compatible = "embedfire,lubancat-2", "rockchip,rk3568";
27 stdout-path = "serial2:1500000n8";
31 compatible = "gpio-leds";
33 user_led: user-led {
[all …]
H A Drk3568-rock-3a.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/leds/common.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/soc/rockchip,vop2.h>
22 stdout-path = "serial2:1500000n8";
25 hdmi-co
[all...]
H A Drk3568-bpi-r2-pro.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Author: Frank Wunderlich <frank-w@public-files.de>
7 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/leds/common.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/soc/rockchip,vop2.h>
15 model = "Bananapi-R2 Pro (RK3568) DDR4 Board";
16 compatible = "rockchip,rk3568-bpi-r2pro", "rockchip,rk3568";
26 stdout-path = "serial2:1500000n8";
[all …]
H A Drk3399pro-vmarc-som.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/rockchip.h>
10 #include <dt-bindings/pwm/pwm.h>
13 compatible = "vamrs,rk3399pro-vmarc-som", "rockchip,rk3399pro";
21 vcc3v3_pcie: vcc-pcie-regulato
[all...]
H A Drk3566-lubancat-1.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/leds/common.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/soc/rockchip,vop2.h>
12 compatible = "embedfire,lubancat-1", "rockchip,rk3566";
21 stdout-pat
[all...]
H A Drk3399-kobol-helios64.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
13 /dts-v1/;
15 #include "rk3399-opp.dtsi"
30 avdd_0v9_s0: avdd-0v9-s0 {
31 compatible = "regulator-fixed";
32 regulator-name = "avdd_0v9_s0";
33 regulator-alway
[all...]
H A Drk3399-rock960.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 #include "rk3399-opp.dtsi"
10 #include <dt-bindings/interrupt-controller/irq.h>
19 sdio_pwrseq: sdio-pwrseq {
20 compatible = "mmc-pwrseq-simple";
22 clock-names = "ext_clock";
23 pinctrl-names = "default";
24 pinctrl-0 = <&wifi_enable_h>;
25 reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
28 vcc12v_dcin: vcc12v-dcin {
[all …]
/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dnvidia,tegra194-pcie.txt4 and thus inherits all the common properties defined in snps,dw-pcie.yaml and
5 snps,dw-pcie-ep.yaml.
10 - power-domains: A phandle to the node that controls power to the respective
20 "include/dt-bindings/power/tegra194-powergate.h" file.
21 - reg: A list of physical base address and length pairs for each set of
22 controller registers. Must contain an entry for each entry in the reg-names
24 - reg-names: Must include the following entries:
26 "config": As per the definition in snps,dw-pcie.yaml
32 - interrupts: A list of interrupt outputs of the controller. Must contain an
33 entry for each entry in the interrupt-names property.
[all …]
H A Dnvidia,tegra194-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Vidya Sagar <vidyas@nvidia.com>
16 inherits all the common properties defined in snps,dw-pcie.yaml. Some of
20 See nvidia,tegra194-pcie-ep.yaml for details on the Endpoint mode device
26 - nvidia,tegra194-pcie
[all …]
H A Drockchip,rk3399-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Lin <shawn.lin@rock-chips.com>
13 - $ref: /schemas/pci/pci-bus.yaml#
14 - $ref: rockchip,rk3399-pcie-common.yaml#
18 const: rockchip,rk3399-pcie
22 reg-names:
24 - const: axi-base
[all …]
H A Drockchip-pcie-host.txt4 - #address-cells: Address representation for root ports, set to <3>
5 - #size-cells: Size representation for root ports, set to <2>
6 - #interrupt-cells: specifies the number of cells needed to encode an
8 - compatible: Should contain "rockchip,rk3399-pcie"
9 - reg: Two register ranges as listed in the reg-names property
10 - reg-names: Must include the following names
11 - "axi-base"
12 - "apb-base"
13 - clocks: Must contain an entry for each entry in clock-names.
14 See ../clocks/clock-bindings.txt for details.
[all …]
H A Drockchip-dw-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip-d
[all...]
H A Dbrcm,stb-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/brcm,stb-pci
[all...]
/freebsd/sys/contrib/device-tree/src/arm64/nvidia/
H A Dtegra234-p3768-0000+p3767-0000.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/linux-event-codes.h>
5 #include <dt-bindings/input/gpio-keys.h>
7 #include "tegra234-p376
[all...]
H A Dtegra234-p3768-0000.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 compatible = "nvidia,p3768-0000";
11 stdout-path = "serial0:115200n8";
23 vcc-supply = <&vdd_1v8_sys>;
24 address-width = <8>;
27 read-only;
32 current-spee
[all...]

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