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Searched full:vlenb (Results 1 – 11 of 11) sorted by relevance

/linux/arch/riscv/kvm/
H A Dvcpu_vector.c26 cntx->vector.vlenb = riscv_v_vsize / 32; in kvm_riscv_vcpu_vector_reset()
102 size_t vlenb = riscv_v_vsize / 32; in kvm_riscv_vcpu_vreg_addr() local
120 case KVM_REG_RISCV_VECTOR_CSR_REG(vlenb): in kvm_riscv_vcpu_vreg_addr()
121 *reg_addr = &cntx->vector.vlenb; in kvm_riscv_vcpu_vreg_addr()
128 if (reg_size != vlenb) in kvm_riscv_vcpu_vreg_addr()
131 (reg_num - KVM_REG_RISCV_VECTOR_REG(0)) * vlenb; in kvm_riscv_vcpu_vreg_addr()
181 if (reg_num == KVM_REG_RISCV_VECTOR_CSR_REG(vlenb)) { in kvm_riscv_vcpu_set_reg_vector()
189 if (reg_val != cntx->vector.vlenb) in kvm_riscv_vcpu_set_reg_vector()
/linux/tools/testing/selftests/riscv/vector/
H A Dvstate_ptrace.c75 ksft_print_msg("vlenb %ld\n", v_regset_hdr->vlenb); in do_parent()
76 data = realloc(data, size + v_regset_hdr->vlenb * 32); in do_parent()
80 v31 = (void *)(data + size + v_regset_hdr->vlenb * 31); in do_parent()
81 size += v_regset_hdr->vlenb * 32; in do_parent()
/linux/Documentation/devicetree/bindings/riscv/
H A Dcpus.yaml40 thead,vlenb: false
115 thead,vlenb:
120 the vlenb CSR is not available.
/linux/arch/riscv/include/uapi/asm/
H A Dptrace.h105 unsigned long vlenb; member
119 unsigned long vlenb; member
/linux/arch/riscv/kernel/
H A Dptrace.c115 ptrace_vstate.vlenb = vstate->vlenb; in riscv_vr_get()
142 if (vstate->vlenb != ptrace_vstate.vlenb) in riscv_vr_set()
H A Dvector.c37 * There are 32 vector registers with vlenb length. in riscv_v_setup_vsize()
39 * If the thead,vlenb property was provided by the firmware, use that in riscv_v_setup_vsize()
57 WARN(1, "RISCV_ISA_V only supports one vlenb on SMP systems"); in riscv_v_setup_vsize()
H A Dcpufeature.c937 u32 vlenb = 0; in has_thead_homogeneous_vlenb() local
939 /* Ignore thead,vlenb property if xtheadvector is not enabled in the kernel */ in has_thead_homogeneous_vlenb()
952 if (of_property_read_u32(cpu_node, "thead,vlenb", &vlenb)) { in has_thead_homogeneous_vlenb()
960 if (prev_vlenb && vlenb != prev_vlenb) { in has_thead_homogeneous_vlenb()
965 prev_vlenb = vlenb; in has_thead_homogeneous_vlenb()
969 thead_vlenb_of = vlenb; in has_thead_homogeneous_vlenb()
1034 pr_warn("Unsupported heterogeneous vlenb detected, vector extension disabled.\n"); in riscv_fill_hwcap_from_ext_list()
/linux/arch/riscv/include/asm/
H A Dvector.h157 dest->vlenb = riscv_v_vsize / 32; in __vstate_csr_save()
163 dest->vlenb = csr_read(CSR_VLENB); in __vstate_csr_save()
433 * riscv_v_vsize contains the value of "32 vector registers with vlenb length"
/linux/arch/riscv/boot/dts/thead/
H A Dth1520.dtsi31 thead,vlenb = <16>;
58 thead,vlenb = <16>;
85 thead,vlenb = <16>;
112 thead,vlenb = <16>;
/linux/tools/testing/selftests/kvm/riscv/
H A Dget-reg-list.c168 /* Enable V extension so that we can get the vlenb register */ in override_vector_reg_size()
175 TEST_FAIL("Can't compute vector register size from zero vlenb\n"); in override_vector_reg_size()
492 case KVM_REG_RISCV_VECTOR_CSR_REG(vlenb): in vector_id_to_str()
493 return "KVM_REG_RISCV_VECTOR_CSR_REG(vlenb)"; in vector_id_to_str()
1015 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_CSR_REG(vlenb),
/linux/arch/riscv/boot/dts/allwinner/
H A Dsun20i-d1s.dtsi31 thead,vlenb = <16>;