Home
last modified time | relevance | path

Searched full:vectors (Results 1 – 25 of 1005) sorted by relevance

12345678910>>...41

/freebsd/contrib/bmake/unit-tests/
H A Dvarmod-hash.mk6 # Test vectors for generating certain hashes. Found by a brute force
9 VECTORS+= 00000000 adjbuqnt
10 VECTORS+= 00000001 beiiyxdp
11 VECTORS+= 00000002 ajriwzqe
12 VECTORS+= 00000004 aimszzcb
13 VECTORS+= 00000008 afffvsgz
14 VECTORS+= 00000010 alkksbun
15 VECTORS+= 00000020 arqeianj
16 VECTORS+= 00000040 acgaltwv
17 VECTORS+= 00000080 addsjxec
[all …]
/freebsd/crypto/libecc/scripts/
H A Dgen_curves_tests.sh45 …-order=6277101735386680763835789423176059013767194773182842284081 --cofactor=1 --add-test-vectors=2
49 …59946667150639794667015087019625940457807714424391721682722368061 --cofactor=1 --add-test-vectors=2
53 …56248762697446949407573529996955224135760342422259061068512044369 --cofactor=1 --add-test-vectors=2
57 …46667946905279627659399113263569398956308152294913554433653942643 --cofactor=1 --add-test-vectors=2
61 …33217197532963996371363321113864768612440380340372808892707005449 --cofactor=1 --add-test-vectors=2
65 …9C976316DA6321 --order=0xE95E4A5F737059DC60DF5991D45029409E60FC09 --cofactor=1 --add-test-vectors=2
69 …299B8F --order=0xC302F41D932A36CDA7A3462F9E9E916B5BE8F1029AC4ACC1 --cofactor=1 --add-test-vectors=2
73 …-order=0xD7C134AA264366862A18302575D0FB98D116BC4B6DDEBCA3A5A7939F --cofactor=1 --add-test-vectors=2
77 …xA9FB57DBA1EEA9BC3E660A909D838D718C397AA3B561A6F7901E0E82974856A7 --cofactor=1 --add-test-vectors=2
81 …7E13C785ED201E065F98FCFA5B68F12A32D482EC7EE8658E98691555B44C59311 --cofactor=1 --add-test-vectors=2
[all …]
/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Daltr,msi-controller.yaml21 - description: Vectors slave port region
33 num-vectors:
34 description: number of vectors
45 - num-vectors
64 num-vectors = <32>;
H A Daltera-pcie-msi.txt9 "vector_slave": vectors slave port region
13 - num-vectors: number of vectors, range 1 to 32.
26 num-vectors = <32>;
/freebsd/contrib/llvm-project/clang/lib/Headers/
H A Dfmaintrin.h21 /// Computes a multiply-add of 128-bit vectors of [4 x float].
41 /// Computes a multiply-add of 128-bit vectors of [2 x double].
62 /// low 32 bits of 128-bit vectors of [4 x float].
91 /// low 64 bits of 128-bit vectors of [2 x double].
119 /// Computes a multiply-subtract of 128-bit vectors of [4 x float].
139 /// Computes a multiply-subtract of 128-bit vectors of [2 x double].
160 /// the low 32 bits of 128-bit vectors of [4 x float].
189 /// the low 64 bits of 128-bit vectors of [2 x double].
217 /// Computes a negated multiply-add of 128-bit vectors of [4 x float].
237 /// Computes a negated multiply-add of 128-bit vectors of [2 x double].
[all …]
/freebsd/sys/dev/cxgbe/firmware/
H A Dt5fw_cfg_fpga.txt26 # 4. MSI-X Vectors: 1088. A complication here is that the PCI-E SR-IOV
28 # same umber of MSI-X Vectors as the base Physical Function.
54 # Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
62 # 8 Ingress Queue/MSI-X Vectors per application function
64 # for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.
176 # NMSIX = 1088 # available MSI-X Vectors
191 # Thus, the number of MSI-X Vectors assigned to the Unified PF will be less
199 # NMSIX_NIC = 32 # NIC MSI-X Interrupt Vectors (FLIQ)
206 # NMSIX_OFLD = 16 # Offload MSI-X Interrupt Vectors (FLIQ)
213 # NMSIX_RDMA = 4 # RDMA MSI-X Interrupt Vectors (FLIQ)
[all …]
H A Dt6fw_cfg_fpga.txt25 # 4. MSI-X Vectors: 1088.
39 # Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
47 # 16 Ingress Queue/MSI-X Vectors per application function
49 # for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.
188 # NMSIX = 1088 # available MSI-X Vectors
203 # Thus, the number of MSI-X Vectors assigned to the Unified PF will be less
211 # NMSIX_NIC = 32 # NIC MSI-X Interrupt Vectors (FLIQ)
218 # NMSIX_OFLD = 16 # Offload MSI-X Interrupt Vectors (FLIQ)
225 # NMSIX_RDMA = 4 # RDMA MSI-X Interrupt Vectors (FLIQ)
236 # NMSIX_ISCSI = 4 # ISCSI MSI-X Interrupt Vectors (FLIQ)
[all …]
H A Dt4fw_cfg_uwire.txt26 # 4. MSI-X Vectors: 1088. A complication here is that the PCI-E SR-IOV
28 # same umber of MSI-X Vectors as the base Physical Function.
54 # Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
62 # 8 Ingress Queue/MSI-X Vectors per application function
64 # for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.
159 # NMSIX = 1088 # available MSI-X Vectors
174 # Thus, the number of MSI-X Vectors assigned to the Unified PF will be less
182 # NMSIX_NIC = 32 # NIC MSI-X Interrupt Vectors (FLIQ)
189 # NMSIX_OFLD = 16 # Offload MSI-X Interrupt Vectors (FLIQ)
196 # NMSIX_RDMA = 4 # RDMA MSI-X Interrupt Vectors (FLIQ)
[all …]
H A Dt5fw_cfg_uwire.txt25 # 4. MSI-X Vectors: 1088.
39 # Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
47 # 8 Ingress Queue/MSI-X Vectors per application function
49 # for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.
194 # NMSIX = 1088 # available MSI-X Vectors
209 # Thus, the number of MSI-X Vectors assigned to the Unified PF will be less
217 # NMSIX_NIC = 32 # NIC MSI-X Interrupt Vectors (FLIQ)
224 # NMSIX_OFLD = 16 # Offload MSI-X Interrupt Vectors (FLIQ)
231 # NMSIX_RDMA = 4 # RDMA MSI-X Interrupt Vectors (FLIQ)
242 # NMSIX_ISCSI = 4 # ISCSI MSI-X Interrupt Vectors (FLIQ)
[all …]
H A Dt6fw_cfg_uwire.txt25 # 4. MSI-X Vectors: 1088.
39 # Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
47 # 16 Ingress Queue/MSI-X Vectors per application function
49 # for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.
211 # NMSIX = 1088 # available MSI-X Vectors
226 # Thus, the number of MSI-X Vectors assigned to the Unified PF will be less
234 # NMSIX_NIC = 32 # NIC MSI-X Interrupt Vectors (FLIQ)
241 # NMSIX_OFLD = 16 # Offload MSI-X Interrupt Vectors (FLIQ)
248 # NMSIX_RDMA = 4 # RDMA MSI-X Interrupt Vectors (FLIQ)
259 # NMSIX_ISCSI = 4 # ISCSI MSI-X Interrupt Vectors (FLIQ)
[all …]
/freebsd/crypto/openssl/test/recipes/30-test_evp_data/
H A Devpciph_sm4.txt9 Title = SM4 test vectors from IETF draft-ribose-cfrg-sm4
52 Title = SM4 GCM test vectors from RFC8998
62 Title = SM4 CCM test vectors from RFC8998
72 Title = SM4 XTS test vectors from GB/T 17964-2021
87 Title = SM4 XTS test vectors, while the XTS mode is standardized in IEEE Std 1619-2007
H A Devpmd_sha.txt110 # Some of the test vectors from the SHS CAVP for FIPS 180-4
140 # Some of the test vectors from the SHS CAVP for FIPS 180-4
174 # Empty input and \xA3x200 vectors are taken from
176 # Others are pairs of "LongMsg" vectors available at
177 # http://csrc.nist.gov/groups/STM/cavp/secure-hashing.html#test-vectors
284 # Following tests are pairs of *last* "VariableOut" vectors from
285 # http://csrc.nist.gov/groups/STM/cavp/secure-hashing.html#test-vectors
307 # Test vectors taken from https://keccak.team/archives.html.
H A Devpciph_aes_stitched.txt1 Title = AES-128-CBC-HMAC-SHA1 test vectors
33 Title = AES-256-CBC-HMAC-SHA1 test vectors
64 Title = AES-128-CBC-HMAC-SHA256 test vectors
96 Title = AES-256-CBC-HMAC-SHA256 test vectors
H A Devpciph_aria.txt14 Title = ARIA test vectors from RFC5794 (and others)
31 # Additional ARIA mode vectors from http://210.104.33.10/ARIA/doc/ARIA-testvector-e.pdf
149 Title = ARIA GCM test vectors from RFC8269
167 Title = ARIA GCM self-generated test vectors
197 Title = ARIA CCM test vectors from IETF draft-ietf-avtcore-aria-srtp-02
H A Devpmac_poly1305.txt84 # test vectors from "The Poly1305-AES message-authentication code"
111 # self-generated vectors exercise "significant" length such that* are handled by different code pat…
191 # test vectors from Google
224 # test vectors from Hanno Bock
256 # test vectors from Andrew Moon - nacl
/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dmips-gic.txt23 - mti,reserved-cpu-vectors : Specifies the list of CPU interrupt vectors
26 - mti,reserved-ipi-vectors : Specifies the range of GIC interrupts that are
52 mti,reserved-cpu-vectors = <7>;
53 mti,reserved-ipi-vectors = <40 8>;
H A Dmti,gic.yaml40 mti,reserved-cpu-vectors:
42 Specifies the list of CPU interrupt vectors to which the GIC may not
53 mti,reserved-ipi-vectors:
115 mti,reserved-cpu-vectors = <7>;
116 mti,reserved-ipi-vectors = <40 8>;
/freebsd/crypto/openssl/doc/man3/
H A DOPENSSL_ia32cap.pod15 stored internally as ten 32-bit capability vectors and for simplicity
16 represented logically below as five 64-bit vectors. This logical
20 Upon toolkit initialization, the capability vectors are populated through
23 initialization is complete, populated vectors are then used to choose
175 of the logical vectors (LV) described above. Each value is delimited by a 'B<:>'.
185 To illustrate, the following will zero all capability bits in logical vectors 1 and further
190 The following will zero all capability bits in logical vectors 2 and further:
207 the rest of the logical vectors unchanged:
/freebsd/share/man/man9/
H A Duio.961 are used to transfer data between buffers and I/O vectors that might
90 The array of I/O vectors to be processed.
94 The number of I/O vectors present.
114 Transfer data from the buffers into the I/O vectors.
116 Transfer data from the I/O vectors into the buffers.
129 requires that the buffer and I/O vectors be accessible without
/freebsd/sys/dev/qat/qat_common/
H A Dadf_isr.c38 u_int *vectors; in adf_enable_msix() local
47 vectors = NULL; in adf_enable_msix()
50 vectors = malloc(num_vectors * sizeof(u_int), in adf_enable_msix()
53 vectors[hw_data->num_banks] = 1; in adf_enable_msix()
65 free(vectors, M_QAT); in adf_enable_msix()
69 if (vectors != NULL) { in adf_enable_msix()
71 pci_remap_msix(info_pci_dev->pci_dev, num_vectors, vectors); in adf_enable_msix()
72 free(vectors, M_QAT); in adf_enable_msix()
/freebsd/secure/lib/libcrypto/man/man3/
H A DOPENSSL_ia32cap.374 stored internally as ten 32\-bit capability vectors and for simplicity
75 represented logically below as five 64\-bit vectors. This logical
79 Upon toolkit initialization, the capability vectors are populated through
82 initialization is complete, populated vectors are then used to choose
215 of the logical vectors (LV) described above. Each value is delimited by a '\fB:\fR'.
225 To illustrate, the following will zero all capability bits in logical vectors 1 and further
230 The following will zero all capability bits in logical vectors 2 and further:
247 the rest of the logical vectors unchanged:
/freebsd/share/man/man4/
H A Dvmd.464 Limits number of Message Signaled Interrupt (MSI) vectors allowed to each
66 VMD can't distinguish MSI vectors of the same device, so there are no
71 Limits number of Extended Message Signaled Interrupt (MSI-X) vectors
73 VMD has limited number of interrupt vectors to map children interrupts into,
/freebsd/sys/dev/ice/
H A Dice_rdma.h72 * @brief Maximum number of MSI-X vectors that will be reserved
74 * Defines the maximum number of MSI-X vectors that an RDMA interface will
75 * have reserved in advance. Does not guarantee that many vectors have
123 * Defines a mapping for MSI-X vectors being requested by the peer RDMA driver
136 * @brief RDMA MSI-X vectors reserved for the peer RDMA driver
138 * Defines the segment of the MSI-X vectors for use by the RDMA driver. These
229 * info about msix vectors
/freebsd/contrib/llvm-project/llvm/include/llvm/Transforms/Utils/
H A DFunctionComparator.h132 /// If both types are vectors, then vector with greater bitwidth is
134 /// If both types are vectors with the same bitwidth, then types
141 /// Stage 4: Types are neither vectors, nor pointers. And they differ.
149 /// [NFCT], [FCT, "others"], [FCT, pointers], [FCT, vectors]
165 /// [NFCT], [FCT, "others"], [FCT, pointers], [FCT, vectors]
187 /// The same logic with vectors, arrays and other possible complex types.
199 /// those should be vectors (if TyA is vector), pointers
204 /// Once again, just because we allow it to vectors and pointers only.
206 /// 2.1. All vectors with equal bitwidth to vector A, has equal bitwidth to
213 /// In another words, for pointers and vectors, w
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InterleavedAccess.cpp71 /// sub vectors of type \p T. Returns the sub-vectors in \p DecomposedVectors.
76 /// returns the transposed-vectors in \p TransposedVectors.
104 /// requires a wide-load instruction \p 'I', a group of interleaved-vectors
134 // Currently, lowering is supported for the following vectors: in isSupported()
136 // 1. Store and load of 4-element vectors of 64 bits on AVX. in isSupported()
137 // 2. Store of 16/32-element vectors of 8 bits on AVX. in isSupported()
139 // 1. Load of 16/32-element vectors of 8 bits on AVX. in isSupported()
241 // genShuffleBland - Creates shuffle according to two vectors.This function is
321 // Assuming we start from the following vectors: in interleave8bitStride4VF8()
361 // Example: Assuming we start from the following vectors: in interleave8bitStride4()
[all …]

12345678910>>...41