Searched +full:vctrl +full:- +full:reg (Results 1 – 4 of 4) sorted by relevance
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)5 * Copyright 2016-2017 Google, Inc8 #include <dt-bindings/input/input.h>9 #include "rk3399-op1.dtsi"18 stdout-path = "serial2:115200n8";27 * - Rails that only connect to the EC (or devices that the EC talks to)29 * - Rails _are_ included if the rails go to the AP even if the AP38 * - The EC controls the enable and the EC always enables a rail as40 * - The rails are actually connected to each other by a jumper and45 ppvar_sys: regulator-ppvar-sys {[all …]
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)3 * Google Gru-Chromebook shared properties8 #include "rk3399-gru.dtsi"11 pp900_ap: regulator-pp900-ap {12 compatible = "regulator-fixed";13 regulator-name = "pp900_ap";16 regulator-always-on;17 regulator-boot-on;18 regulator-min-microvolt = <900000>;19 regulator-max-microvolt = <900000>;[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later3 * at91-tse850-3.dts - Device Tree file for the Axentia TSE-850 3.0 board9 /dts-v1/;10 #include <dt-bindings/pwm/pwm.h>11 #include "at91-linea.dtsi"14 model = "Axentia TSE-850 3.0";19 compatible = "fixed-clock";21 #clock-cells = <0>;22 clock-frequency = <16000000>;23 clock-output-names = "sck";[all …]
1 // SPDX-License-Identifier: GPL-2.0-only16 * Note that IRQs 0-31 are special - they are local to each CPU.18 * registers are banked per-cpu for these sources.42 #include <linux/irqchip/arm-gic.h>50 #include "irq-gic-common.h"140 return raw_cpu_read(*base->percpu_base); in __get_base()142 return base->common_base; in __get_base()145 #define gic_data_dist_base(d) __get_base(&(d)->dist_base)146 #define gic_data_cpu_base(d) __get_base(&(d)->cpu_base)148 #define gic_data_dist_base(d) ((d)->dist_base.common_base)[all …]