Home
last modified time | relevance | path

Searched +full:vbus +full:- +full:supply (Results 1 – 25 of 607) sorted by relevance

12345678910>>...25

/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dnvidia,tegra210-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xus
[all...]
H A Dnvidia,tegra186-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra186-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
H A Dnvidia,tegra124-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
H A Dnvidia,tegra194-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra194-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
H A Dsamsung,usb3-drd-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/samsung,usb3-drd-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Marek Szyprowski <m.szyprowski@samsung.com>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
15 For samsung,exynos5250-usbdrd-phy and samsung,exynos5420-usbdrd-phy
18 0 - UTMI+ type phy,
19 1 - PIPE3 type phy.
[all …]
H A Dnvidia,tegra124-xusb-padctl.txt11 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
12 super-speed USB. Other lanes are for various types of low-speed, full-speed
13 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
14 contains a software-configurable mux that sits between the I/O controller
17 In addition to per-lane configuration, USB 3.0 ports may require additional
18 settings on a per-board basis.
20 Pads will be represented as children of the top-level XUSB pad controller
23 PHY bindings, as described by the phy-bindings.txt file in this directory.
30 for the USB signal, the VBUS power supply, the USB 2.0 companion port for
34 --------------------
[all …]
H A Dallwinner,sun6i-a31-usb-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun6i-a31-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
18 const: allwinner,sun6i-a31-usb-phy
22 - description: PHY Control registers
23 - description: PHY PMU1 registers
[all …]
H A Dallwinner,sun4i-a10-usb-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun4i-a10-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
19 - allwinner,sun4i-a10-usb-phy
20 - allwinner,sun7i-a20-usb-phy
24 - description: PHY Control registers
[all …]
H A Dallwinner,sun8i-a83t-usb-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun8i-a83t-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
18 const: allwinner,sun8i-a83t-usb-phy
22 - description: PHY Control registers
23 - description: PHY PMU1 registers
[all …]
H A Dallwinner,sun50i-a64-usb-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun50i-a64-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
19 - allwinner,sun20i-d1-usb-phy
20 - allwinner,sun50i-a64-usb-phy
24 - description: PHY Control registers
[all …]
H A Dallwinner,sun8i-a23-usb-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun8i-a23-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
19 - allwinner,sun8i-a23-usb-phy
20 - allwinner,sun8i-a33-usb-phy
24 - description: PHY Control registers
[all …]
/freebsd/sys/contrib/device-tree/Bindings/usb/
H A Dusb-nop-xceiv.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/usb-nop-xceiv.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
14 const: usb-nop-xceiv
19 clock-names:
22 clock-frequency: true
24 '#phy-cells':
27 vcc-supply:
[all …]
H A Dqcom,pmic-typec.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/qcom,pmic-typec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm PMIC based USB Type-C block
10 - Bryan O'Donoghue <bryan.odonoghue@linaro.org>
13 Qualcomm PMIC Type-C block
18 - enum:
19 - qcom,pmi632-typec
20 - qcom,pm8150b-typec
[all …]
H A Dfcs,fusb302.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Fairchild FUSB302 Type-C Port controller
10 - Rob Herring <robh@kernel.org>
22 vbus-supply:
23 description: VBUS power supply
27 $ref: /schemas/connector/usb-connector.yaml#
31 - compatible
32 - reg
[all …]
H A Dusb-nop-xceiv.txt4 - compatible: should be usb-nop-xceiv
5 - #phy-cells: Must be 0
8 - clocks: phandle to the PHY clock. Use as per Documentation/devicetree
9 /bindings/clock/clock-bindings.txt
10 This property is required if clock-frequency is specified.
12 - clock-names: Should be "main_clk"
14 - clock-frequency: the clock frequency (in Hz) that the PHY clock must
17 - vcc-supply: phandle to the regulator that provides power to the PHY.
19 - reset-gpios: Should specify the GPIO for reset.
21 - vbus-detect-gpio: should specify the GPIO detecting a VBus insertion
[all …]
H A Dmediatek,mtk-xhci.txt6 the second one supports dual-role mode, and the host is based on xHCI
11 ------------------------------------------------------------------------
14 - compatible : should be "mediatek,<soc-model>-xhci", "mediatek,mtk-xhci",
15 soc-model is the name of SoC, such as mt8173, mt2712 etc, when using
16 "mediatek,mtk-xhci" compatible string, you need SoC specific ones in
18 - "mediatek,mt8173-xhci"
19 - reg : specifies physical base address and size of the registers
20 - reg-names: should be "mac" for xHCI MAC and "ippc" for IP port control
21 - interrupts : interrupt used by the controller
22 - power-domains : a phandle to USB power domain node to control USB's
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt2712-evb.dts5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
14 chassis-type = "embedded";
15 compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
27 stdout-path = "serial0:921600n8";
30 cpus_fixed_vproc0: regulator-vproc-buck0 {
31 compatible = "regulator-fixed";
32 regulator-name = "vproc_buck0";
33 regulator-min-microvolt = <1000000>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/nvidia/
H A Dtegra194-p2888.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/mfd/max77620.h>
27 stdout-path = "serial0:115200n8";
34 phy-reset-gpios = <&gpio TEGRA194_MAIN_GPIO(G, 5) GPIO_ACTIVE_LOW>;
35 phy-handle = <&phy>;
36 phy-mode = "rgmii-id";
39 #address-cells = <1>;
40 #size-cells = <0>;
42 phy: ethernet-phy@0 {
43 compatible = "ethernet-phy-ieee802.3-c22";
[all …]
H A Dtegra234-p3740-0002.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/sound/rt5640.h>
6 compatible = "nvidia,p3740-0002";
15 dai-format = "i2s";
16 remote-endpoint = <&rt5640_ep>;
26 bitclock-master;
27 frame-master;
36 rt5640: audio-code
[all...]
H A Dtegra234-p3701.dtsi1 // SPDX-License-Identifier: GPL-2.0
41 dma-controller@2930000 {
45 interrupt-controller@2a40000 {
58 vcc-supply = <&vdd_1v8_hs>;
59 address-width = <8>;
62 read-only;
70 compatible = "jedec,spi-nor";
72 spi-max-frequency = <102000000>;
73 spi-tx-bus-width = <4>;
74 spi-rx-bus-width = <4>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nvidia/
H A Dtegra124-apalis-v1.2-eval.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright 2016-2018 Toradex AG
6 /dts-v1/;
8 #include <dt-bindings/input/input.h>
9 #include "tegra124-apalis-v1.2.dtsi"
13 compatible = "toradex,apalis-tk1-v
[all...]
H A Dtegra124-apalis-eval.dts1 // SPDX-License-Identifier: GPL-2.0 OR X11
3 * Copyright 2016-2019 Toradex AG
6 /dts-v1/;
8 #include <dt-bindings/input/input.h>
9 #include "tegra124-apalis.dtsi"
13 compatible = "toradex,apalis-tk1-eval", "toradex,apalis-tk
[all...]
H A Dtegra30-apalis-v1.1-eval.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
5 #include "tegra30-apalis-v1.1.dtsi"
9 compatible = "toradex,apalis_t30-v1.1-eval", "toradex,apalis_t30-eva
[all...]
H A Dtegra30-apalis-eval.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
5 #include "tegra30-apalis.dtsi"
9 compatible = "toradex,apalis_t30-eval", "toradex,apalis_t30",
23 stdout-path = "serial0:115200n8";
46 hdmi-supply
[all...]
H A Dtegra30-colibri-eval-v3.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
5 #include "tegra30-colibri.dtsi"
9 compatible = "toradex,colibri_t30-eval-v3", "toradex,colibri_t30",
22 stdout-path = "serial0:115200n8";
35 hdmi-suppl
[all...]

12345678910>>...25