Searched full:usbphy1 (Results 1 – 25 of 44) sorted by relevance
12
73 &usbphy1 {
125 &usbphy1 {
143 &usbphy1 {
49 fsl,usbphy = <&usbphy1>;65 usbphy1: usbphy@5b100000 { label
144 &usbphy1 {
42 usbphy1: usbphy@8007e000 { label
119 &usbphy1 {
152 &usbphy1 {
159 &usbphy1 {
38 usbphy1 = &usbphy1;1276 usbphy1: usbphy@8007e000 { label1306 fsl,usbphy = <&usbphy1>;
256 &usbphy1 {
311 &usbphy1 {
348 &usbphy1 {
31 - "clk_usbphy1_480m" - output clock of the pll in the usbphy1
101 usbphy1: phy@a00800 {
69 &usbphy1 {
184 &usbphy1 {
127 usbphy1: usbphy-1 { label350 fsl,usbphy = <&usbphy1>;
314 &usbphy1 {
48 #define USBPHY1 34 macro
169 &usbphy1 {
362 &usbphy1 {
309 &usbphy1 {
348 phys = <&usbphy1>;360 phys = <&usbphy1>;365 usbphy1: phy@a00800 { label
254 * usbphy1 and usbphy2 are implemented as dummy gates using reserve in imx6sl_clocks_init()260 hws[IMX6SL_CLK_USBPHY1] = imx_clk_hw_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20); in imx6sl_clocks_init()