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12

/linux/Documentation/devicetree/bindings/usb/
H A Damlogic,meson-g12a-usb-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/amlogic,meson-g12a-usb-ctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Neil Armstrong <neil.armstrong@linaro.org>
14 The Amlogic G12A embeds a DWC3 USB IP Core configured for USB2 and USB3
15 in host-only mode, and a DWC2 IP Core configured for USB2 peripheral mode
18 A glue connects the DWC3 core to USB2 PHYs and optionally to an USB3 PHY.
20 One of the USB2 PHYs can be re-routed in peripheral mode to a DWC2 USB IP.
25 The Amlogic A1 embeds a DWC3 USB IP Core configured for USB2 in
[all …]
/linux/drivers/phy/nuvoton/
H A Dphy-ma35d1-usb2.c1 // SPDX-License-Identifier: GPL-2.0
19 #define PHY0POR BIT(0) /* PHY Power-On Reset Control Bit */
21 #define PHY0COMN BIT(2) /* PHY Common Block Power-Down Control */
36 ret = clk_prepare_enable(p_phy->clk); in ma35_usb_phy_power_on()
38 dev_err(p_phy->dev, "Failed to enable PHY clock: %d\n", ret); in ma35_usb_phy_power_on()
42 regmap_read(p_phy->sysreg, MA35_SYS_REG_USBPMISCR, &val); in ma35_usb_phy_power_on()
45 * USB PHY0 is in operation mode already in ma35_usb_phy_power_on()
48 ret = regmap_read_poll_timeout(p_phy->sysreg, MA35_SYS_REG_USBPMISCR, val, in ma35_usb_phy_power_on()
55 * reset USB PHY0. in ma35_usb_phy_power_on()
56 * wait until USB PHY0 60 MHz UTMI Interface Clock ready in ma35_usb_phy_power_on()
[all …]
/linux/arch/powerpc/boot/dts/fsl/
H A Dp1020utm-pc.dtsi2 * P1020 UTM-PC Device Tree Source stub (no addresses or top-level ranges)
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
64 /* 512KB for u-boot Bootloader Image */
65 /* 512KB for u-boot Environment Variables */
67 label = "NOR U-Boot Image";
68 read-only;
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H A Dp1020mbg-pc.dtsi2 * P1020 MBG-PC Device Tree Source stub (no addresses or top-level ranges)
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
66 label = "NOR Vitesse-7385 Firmware";
67 read-only;
72 /* 512KB for u-boot Bootloader Image */
73 /* 512KB for u-boot Environment Variables */
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H A Dp1020rdb-pc.dtsi2 * P1020 RDB-PC Device Tree Source stub (no addresses or top-level ranges)
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
48 label = "NOR Vitesse-7385 Firmware";
49 read-only;
72 /* 512KB for u-boot Bootloader Image */
73 /* 512KB for u-boot Environment Variables */
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H A Dp1025rdb.dtsi2 * P1025 RDB Device Tree Source stub (no addresses or top-level ranges)
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
48 label = "NOR Vitesse-7385 Firmware";
49 read-only;
72 /* 512KB for u-boot Bootloader Image */
73 /* 512KB for u-boot Environment Variables */
[all …]
H A Dp1020rdb.dtsi2 * P1020 RDB Device Tree Source stub (no addresses or top-level ranges)
4 * Copyright 2011-2012 Freescale Semiconductor Inc.
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
48 label = "NOR (RO) Vitesse-7385 Firmware";
49 read-only;
56 read-only;
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/linux/drivers/usb/dwc3/
H A Ddwc3-meson-g12a.c1 // SPDX-License-Identifier: GPL-2.0
11 * - Control registers for each USB2 Ports
12 * - Control registers for the USB PHY layer
13 * - SuperSpeed PHY can be enabled only if port is used
14 * - Dynamic OTG switching with ID change interrupt
33 /* USB2 Ports Control Registers, offsets are per-port */
120 "usb2-phy0", "usb2-phy1", "usb2-phy2",
124 "usb2-phy0", "usb2-phy1", "usb3-phy0",
133 * correctly when only the "usb2-phy1" phy is specified on-par with the
137 "usb2-phy0", "usb2-phy1"
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/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-g12b-s922x-khadas-vim3.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "meson-g12b-s922x.dtsi"
11 #include "meson-khadas-vim3.dtsi"
12 #include "meson-g12b-khadas-vim3.dtsi"
19 * The VIM3 on-board MCU can mux the PCIe/USB3.0 shared differential
39 phy-names = "usb2-phy0", "usb2-phy1";
H A Dmeson-g12b-a311d-khadas-vim3.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "meson-g12b-a311d.dtsi"
11 #include "meson-khadas-vim3.dtsi"
12 #include "meson-g12b-khadas-vim3.dtsi"
19 * The VIM3 on-board MCU can mux the PCIe/USB3.0 shared differential
39 phy-names = "usb2-phy0", "usb2-phy1";
H A Dmeson-sm1-khadas-vim3l.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include "meson-sm1.dtsi"
10 #include "meson-khadas-vim3.dtsi"
11 #include <dt-bindings/sound/meson-g12a-tohdmitx.h>
17 vddcpu: regulator-vddcpu {
21 compatible = "pwm-regulator";
23 regulator-name = "VDDCPU";
24 regulator-min-microvolt = <690000>;
25 regulator-max-microvolt = <1050000>;
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H A Dmeson-sm1-odroid-hc4.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "meson-sm1-odroid.dtsi"
11 compatible = "hardkernel,odroid-hc4", "amlogic,sm1";
12 model = "Hardkernel ODROID-HC4";
19 fan0: pwm-fan {
20 compatible = "pwm-fan";
21 #cooling-cells = <2>;
22 cooling-levels = <0 120 170 220>;
27 compatible = "gpio-leds";
[all …]
H A Dmeson-g12b-bananapi-cm4.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include "meson-g12b-a311d.dtsi"
7 #include <dt-bindings/gpio/meson-g12a-gpio.h>
16 stdout-path = "serial0:115200n8";
19 emmc_pwrseq: emmc-pwrseq {
20 compatible = "mmc-pwrseq-emmc";
21 reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
29 sdio_pwrseq: sdio-pwrseq {
30 compatible = "mmc-pwrseq-simple";
31 reset-gpios = <&gpio GPIOAO_6 GPIO_ACTIVE_LOW>;
[all …]
/linux/arch/arm/boot/dts/marvell/
H A Darmada-375-db.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * (DB-88F6720)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 /dts-v1/;
13 #include <dt-bindings/gpio/gpio.h>
14 #include "armada-375.dtsi"
18 compatible = "marvell,a375-db", "marvell,armada375";
21 stdout-path = "serial0:115200n8";
57 pinctrl-0 = <&spi0_pins>;
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/linux/arch/arm/boot/dts/intel/ixp/
H A Dintel-ixp42x-usrobotics-usr8200.dts1 // SPDX-License-Identifier: ISC
4 * VPN and NAS. Based on know-how from Peter Denison.
10 /dts-v1/;
12 #include "intel-ixp42x.dtsi"
13 #include <dt-bindings/input/input.h>
18 #address-cells = <1>;
19 #size-cells = <1>;
28 stdout-path = "uart1:115200n8";
38 compatible = "gpio-leds";
39 ieee1394_led: led-1394 {
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/linux/arch/arm64/boot/dts/ti/
H A Dk3-am654-pcie-usb2.dtso1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * DT overlay for SERDES personality card: 2lane PCIe + USB2.0 Host on AM654 EVM
5 * Copyright (C) 2018-2024 Texas Instruments Incorporated - https://www.ti.com/
8 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/phy/phy-am654-serdes.h>
13 #include "k3-pinctrl.h"
16 assigned-clocks = <&k3_clks 153 4>,
19 assigned-clock-parents = <&k3_clks 153 8>,
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/linux/arch/arm/boot/dts/st/
H A Dstm32h743i-eval.dts2 * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
4 * This file is dual-licensed: you can use it either under the terms
43 /dts-v1/;
45 #include "stm32h7-pinctrl.dtsi"
48 model = "STMicroelectronics STM32H743i-EVAL board";
49 compatible = "st,stm32h743i-eval", "st,stm32h743";
53 stdout-path = "serial0:115200n8";
65 vdda: regulator-vdda {
66 compatible = "regulator-fixed";
67 regulator-name = "vdda";
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H A Dstm32mp15xx-dhcor-testbench.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
17 stdout-path = "serial0:115200n8";
20 sd_switch: regulator-sd_switch {
21 compatible = "regulator-gpio";
22 regulator-name = "sd_switch";
23 regulator-min-microvolt = <1800000>;
24 regulator-max-microvolt = <2900000>;
25 regulator-type = "voltage";
26 regulator-always-on;
29 gpios-states = <0>;
[all …]
/linux/arch/powerpc/boot/dts/
H A Dasp834x-redboot.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
12 compatible = "analogue-and-micro,asp8347e";
13 #address-cells = <1>;
14 #size-cells = <1>;
24 #address-cells = <1>;
25 #size-cells = <0>;
30 d-cache-line-size = <32>;
31 i-cache-line-size = <32>;
32 d-cache-size = <32768>;
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H A Dmpc5125twr.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Reworked by Matteo Facchinetti (engineering@sirius-es.it)
11 #include <dt-bindings/clock/mpc512x-clock.h>
13 /dts-v1/;
18 #address-cells = <1>;
19 #size-cells = <1>;
20 interrupt-parent = <&ipic>;
29 #address-cells = <1>;
30 #size-cells = <0>;
35 d-cache-line-size = <0x20>; // 32 bytes
[all …]
/linux/arch/arm64/boot/dts/marvell/
H A Darmada-3720-db.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * (DB-88F3720-DDR3)
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
14 /dts-v1/;
16 #include <dt-bindings/gpio/gpio.h>
17 #include "armada-372x.dtsi"
20 model = "Marvell Armada 3720 Development Board DB-88F3720-DDR3";
21 compatible = "marvell,armada-3720-db", "marvell,armada3720", "marvell,armada3710";
24 stdout-path = "serial0:115200n8";
32 exp_usb3_vbus: usb3-vbus {
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/linux/arch/riscv/boot/dts/starfive/
H A Djh7110-pine64-star64.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 /dts-v1/;
7 #include "jh7110-common.dtsi"
18 starfive,tx-use-rgmii-clk;
19 assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
20 assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
25 phy-handle = <&phy1>;
26 phy-mode = "rgmii-id";
27 starfive,tx-use-rgmii-clk;
28 assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>;
[all …]
/linux/arch/arm/boot/dts/microchip/
H A Dat91-sama5d4_ma5d4evk.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
6 /dts-v1/;
7 #include "at91-sama5d4_ma5d4.dtsi"
14 stdout-path = "serial3:115200n8";
19 atmel,vbus-gpio = <&pioE 31 GPIO_ACTIVE_HIGH>;
20 pinctrl-names = "default";
21 pinctrl-0 = <&pinctrl_usba_vbus>;
26 num-ports = <3>;
27 atmel,vbus-gpio = <0
34 usb2: usb@600000 { label
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/linux/drivers/phy/allwinner/
H A Dphy-sun4i-usb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2014-2015 Hans de Goede <hdegoede@redhat.com>
18 #include <linux/extcon-provider.h>
27 #include <linux/phy/phy-sun4i-usb.h>
79 /* A83T specific control bits for PHY0 */
128 /* phy0 / otg related variables */
145 container_of((phy), struct sun4i_usb_phy_data, phys[(phy)->index])
153 iscr = readl(data->base + REG_ISCR); in sun4i_usb_phy0_update_iscr()
156 writel(iscr, data->base + REG_ISCR); in sun4i_usb_phy0_update_iscr()
183 u32 temp, usbc_bit = BIT(phy->index * 2); in sun4i_usb_phy_write()
[all …]
/linux/arch/arm64/boot/dts/renesas/
H A Dsalvator-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for common parts of Salvator-X board variants
5 * Copyright (C) 2015-2016 Renesas Electronics Corp.
9 * SSI-AK4613
31 #include <dt-bindings/gpio/gpio.h>
32 #include <dt-bindings/input/input.h>
54 stdout-path = "serial0:115200n8";
57 audio_clkout: audio-clkout {
60 * but needed to avoid cs2000/rcar_sound probe dead-lock
62 compatible = "fixed-clock";
[all …]

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