| /linux/Documentation/devicetree/bindings/phy/ |
| H A D | phy-hisi-inno-usb2.txt | 1 Device tree bindings for HiSilicon INNO USB2 PHY
4 - compatible: Should be one of the following strings:
5 "hisilicon,inno-usb2-phy",
6 "hisilicon,hi3798cv200-usb2-phy".
7 - reg: Should be the address space for PHY configuration register in peripheral
9 - clocks: The phandle and clock specifier pair for INNO USB2 PHY device
11 - resets: The phandle and reset specifier pair for INNO USB2 PHY device reset
13 - #address-cells: Must be 1.
14 - #size-cells: Must be 0.
16 The INNO USB2 PHY device should be a child node of peripheral controller that
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| H A D | phy-lantiq-rcu-usb2.txt | 9 -------------------------------------------------------------------------------
11 - compatible : Should be one of
12 "lantiq,ase-usb2-phy"
13 "lantiq,danube-usb2-phy"
14 "lantiq,xrx100-usb2-phy"
15 "lantiq,xrx200-usb2-phy"
16 "lantiq,xrx300-usb2-phy"
17 - reg : Defines the following sets of registers in the parent
18 syscon device
19 - Offset of the USB PHY configuration register
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| H A D | ti-phy.txt | 6 - compatible: Should be one of
7 "ti,control-phy-otghs" - if it has otghs_control mailbox register as on OMAP4.
8 "ti,control-phy-usb2" - if it has Power down bit in control_dev_conf register
10 "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control
12 "ti,control-phy-pcie" - for pcie to support external clock for pcie and to
15 "ti,control-phy-usb2-dra7" - if it has power down register like USB2 PHY on
17 "ti,control-phy-usb2-am437" - if it has power down register like USB2 PHY on
19 - reg : register ranges as listed in the reg-names property
20 - reg-names: "otghs_control" for control-phy-otghs
21 "power", "pcie_pcs" and "control_sma" for control-phy-pcie
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| H A D | nvidia,tegra210-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
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| H A D | nvidia,tegra124-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
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| /linux/drivers/phy/tegra/ |
| H A D | xusb-tegra186.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved.
21 #define HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? (11 + (x - 1) * 6) : 0)
42 #define PORTX_CAP_SHIFT(x) ((x) * 4)
67 #define PORTX_SPEED_SUPPORT_SHIFT(x) ((x) * 4)
101 #define HSIC_PD_RX_DATA0 BIT(4)
123 #define UHSIC_LINE_DEB_CNT(x) (((x) & 0xf) << 4)
126 #define XUSB_AO_UTMIP_TRIGGERS(x) (0x40 + (x) * 4)
131 #define XUSB_AO_UHSIC_TRIGGERS(x) (0x60 + (x) * 4)
134 #define HSIC_CAP_CFG BIT(4)
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| H A D | xusb-tegra210.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
27 ((x) ? (11 + ((x) - 1) * 6) : 0)
44 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_DISABLED(x) (0x0 << ((x) * 4))
45 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_HOST(x) (0x1 << ((x) * 4))
46 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_DEVICE(x) (0x2 << ((x) * 4))
47 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_OTG(x) (0x3 << ((x) * 4))
48 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_MASK(x) (0x3 << ((x) * 4))
51 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(x) (1 << (((x) * 5) + 4))
144 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA0 (1 << 4)
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| /linux/arch/arm64/boot/dts/nvidia/ |
| H A D | tegra234-p3768-0000+p3767.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/input/linux-event-codes.h>
4 #include <dt-bindings/input/gpio-keys.h>
6 #include "tegra234-p3767.dtsi"
17 stdout-path = "serial0:115200n8";
22 compatible = "nvidia,tegra194-hsuart";
23 reset-names = "serial";
28 compatible = "nvidia,tegra194-hsuart";
29 reset-names = "serial";
41 vcc-supply = <&vdd_1v8_sys>;
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| H A D | tegra186-p3509-0000+p3636-0001.dts | 1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/linux-event-codes.h>
5 #include <dt-bindings/input/gpio-keys.h>
6 #include <dt-bindings/mfd/max77620.h>
12 compatible = "nvidia,p3509-0000+p3636-0001", "nvidia,tegra186";
30 stdout-path = "serial0:115200n8";
41 phy-reset-gpios = <&gpio_aon TEGRA186_AON_GPIO(AA, 6) GPIO_ACTIVE_LOW>;
42 phy-handle = <&phy>;
43 phy-mode = "rgmii-id";
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| H A D | tegra194-p2972-0000.dts | 1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/linux-event-codes.h>
5 #include <dt-bindings/input/gpio-keys.h>
7 #include "tegra194-p2888.dtsi"
11 compatible = "nvidia,p2972-0000", "nvidia,tegra194";
24 #address-cells = <1>;
25 #size-cells = <0>;
31 remote-endpoint = <&xbar_i2s1_ep>;
39 dai-format = "i2s";
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| H A D | tegra210-p3450-0000.dts | 1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/gpio-keys.h>
5 #include <dt-bindings/input/linux-event-codes.h>
6 #include <dt-bindings/mfd/max77620.h>
12 compatible = "nvidia,p3450-0000", "nvidia,tegra210";
22 stdout-path = "serial0:115200n8";
33 hvddio-pex-supply = <&vdd_1v8>;
34 dvddio-pex-supply = <&vdd_pex_1v05>;
35 vddio-pex-ctl-supply = <&vdd_1v8>;
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| /linux/Documentation/firmware-guide/acpi/ |
| H A D | intel-pmc-mux.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 Intel North Mux-Agent
10 North Mux-Agent is a function of the Intel PMC firmware that is supported on
13 platforms that allow the mux-agent to be configured from the operating system
14 have an ACPI device object (node) with HID "INTC105C" that represents it.
16 The North Mux-Agent (aka. Intel PMC Mux Control, or just mux-agent) driver
18 (drivers/platform/x86/intel_scu_ipc.c). The driver registers with the USB Type-C
19 Mux Class which allows the USB Type-C Controller and Interface drivers to
22 Device modes. The driver is located here: drivers/usb/typec/mux/intel_pmc_mux.c.
28 -------
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| /linux/Documentation/devicetree/bindings/mips/lantiq/ |
| H A D | rcu.txt | 4 This binding describes the RCU (reset controller unit) multifunction device,
5 where each sub-device has its own set of registers.
7 The RCU register range is used for multiple purposes. Mostly one device
14 -------------------------------------------------------------------------------
16 - compatible : The first and second values must be:
17 "lantiq,xrx200-rcu", "simple-mfd", "syscon"
18 - reg : The address and length of the system control registers
21 -------------------------------------------------------------------------------
24 compatible = "lantiq,xrx200-rcu", "simple-mfd", "syscon";
27 big-endian;
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| /linux/drivers/usb/gadget/udc/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
7 # NOTE: Gadget support ** DOES NOT ** depend on host-side CONFIG_USB !!
9 # - Host systems (like PCs) need CONFIG_USB (with "A" jacks).
10 # - Peripherals (like PDAs) need CONFIG_USB_GADGET (with "B" jacks).
11 # - Some systems have both kinds of controllers.
13 # With help from a special transceiver and a "Mini-AB" jack, systems with
14 # both kinds of controller can also support "USB On-the-Go" (CONFIG_USB_OTG).
22 # - integrated/SOC controllers first
23 # - licensed IP used in both SOC and discrete versions
24 # - discrete ones (including all PCI-only controllers)
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| /linux/drivers/phy/marvell/ |
| H A D | phy-mvebu-a3700-utmi.c | 1 // SPDX-License-Identifier: GPL-2.0
38 #define PHY_PU_OTG BIT(4)
42 #define PHY_PD_EN BIT(4)
59 * struct mvebu_a3700_utmi_caps - PHY capabilities
62 * - The UTMI PHY wired to the USB3/USB2 controller (otg)
63 * - The UTMI PHY wired to the USB2 controller (host only)
72 * struct mvebu_a3700_utmi - PHY driver data
89 struct device *dev = &phy->dev; in mvebu_a3700_utmi_phy_power_on()
90 int usb32 = utmi->caps->usb32; in mvebu_a3700_utmi_phy_power_on()
98 reg = readl(utmi->regs + USB2_PHY_PLL_CTRL_REG0); in mvebu_a3700_utmi_phy_power_on()
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| /linux/arch/arm/boot/dts/broadcom/ |
| H A D | bcm47094-dlink-dir-890l.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Device tree for D-Link DIR-890L
4 * D-Link calls this board "WRGAC36"
5 * this router has the same looks and form factor as D-Link DIR-885L.
7 * Some differences from DIR-885L include a separate USB2 port, separate LEDs
8 * for USB2 and USB3, a separate VCC supply for the USB2 slot and no
10 * PCB) so this device is a pure router. Also the LAN ports are in the right
13 * Based on the device tree for DIR-885L
18 /dts-v1/;
21 #include "bcm5301x-nand-cs0-bch1.dtsi"
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| /linux/arch/arm/boot/dts/nvidia/ |
| H A D | tegra124-nyan.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/input/input.h>
3 #include <dt-bindings/thermal/thermal.h>
14 stdout-path = "serial0:115200n8";
18 * Note that recent version of the device tree compiler (starting with
20 * missing a unit-address. However, the bootloader on these Chromebook
22 * Adding the unit-address causes the bootloader to create a /memory
24 * turn leads the kernel to believe that the device has 2 GiB of
34 /delete-node/ memory@80000000;
40 vdd-supply = <&vdd_3v3_hdmi>;
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| /linux/drivers/usb/host/ |
| H A D | xhci-port.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* PORTSC - Port Status and Control Register - port_status_base bitmasks */
4 /* true: device connected */
9 /* true: port has an over-current condition */
12 #define PORT_RESET (1 << 4)
13 /* Port Link State - bits 5:8
34 /* bits 10:13 indicate device speed:
35 * 0 - undefined speed - port hasn't be initialized by a reset yet
36 * 1 - full speed
37 * 2 - low speed
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| /linux/Documentation/driver-api/media/drivers/ |
| H A D | dvb-usb.rst | 1 .. SPDX-License-Identifier: GPL-2.0
3 Idea behind the dvb-usb-framework
11 #) **deprecated:** Newer DVB USB drivers should use the dvb-usb-v2 framework.
13 In March 2005 I got the new Twinhan USB2.0 DVB-T device. They provided specs
18 dibusb-driver would be a complete mess afterwards. So I decided to do it in a
19 different way: With the help of a dvb-usb-framework.
23 - Transport Stream URB handling in conjunction with dvb-demux-feed-control
25 - registering the device for the DVB-API
26 - registering an I2C-adapter if applicable
27 - remote-control/input-device handling
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| /linux/Documentation/ABI/testing/ |
| H A D | sysfs-bus-pci-drivers-ehci_hcd | 7 PCI-based EHCI USB controllers (i.e., high-speed USB-2.0
9 "companion" full/low-speed USB-1.1 controllers. When a
10 high-speed device is plugged in, the connection is routed
11 to the EHCI controller; when a full- or low-speed device
15 Sometimes you want to force a high-speed device to connect
23 For example: To force the high-speed device attached to
24 port 4 on bus 2 to run at full speed::
26 echo 4 >/sys/bus/usb/devices/usb2/../companion
28 To return the port to high-speed operation::
30 echo -4 >/sys/bus/usb/devices/usb2/../companion
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| /linux/arch/powerpc/boot/dts/fsl/ |
| H A D | p5040si-post.dtsi | 2 * P5040 Silicon/SoC Device Tree Source (post include)
4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10000 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10000 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10000 0>;
51 compatible = "fsl,p5040-elbc", "fsl,elbc", "simple-bus";
53 #address-cells = <2>;
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| /linux/Documentation/devicetree/bindings/usb/ |
| H A D | mediatek,mtk-xhci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/mediatek,mtk-xhci.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 - $ref: usb-xhci.yaml
19 case 2: supports dual-role mode, and the host is based on xHCI driver.
25 - enum:
26 - mediatek,mt2701-xhci
27 - mediatek,mt2712-xhci
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| /linux/include/linux/phy/ |
| H A D | omap_control_phy.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * omap_control_phy.h - Header file for the PHY part of control module.
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
17 OMAP_CTRL_TYPE_DRA7USB2, /* USB2 PHY, power and power_aux e.g. DRA7 */
18 OMAP_CTRL_TYPE_AM437USB2, /* USB2 PHY, power e.g. AM437x */
22 struct device *dev;
47 #define OMAP_CTRL_DEV_IDDIG BIT(4)
69 void omap_control_phy_power(struct device *dev, int on);
70 void omap_control_usb_set_mode(struct device *dev,
72 void omap_control_pcie_pcs(struct device *dev, u8 delay);
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| /linux/drivers/phy/amlogic/ |
| H A D | phy-meson-g12a-usb2.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Meson G12A USB2 PHY driver
29 #define PHY_CTRL_R3_DISC_THRESH GENMASK(7, 4)
70 #define PHY_CTRL_R14_PG_RSTN BIT(4)
120 #define PHY_CTRL_R20_USB2_OTG_VBUSDET_EN BIT(4)
139 #define PHY_CTRL_R21_USB2_OTG_ACA_TRIM_1_0 GENMASK(5, 4)
155 struct device *dev;
165 .reg_stride = 4,
175 ret = clk_prepare_enable(priv->clk); in phy_meson_g12a_usb2_init()
179 ret = reset_control_reset(priv->reset); in phy_meson_g12a_usb2_init()
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| /linux/arch/arm/boot/dts/microchip/ |
| H A D | at91-wb45n.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * at91-wb45n.dtsi - Device Tree file for WB45NBT board
12 model = "Laird Workgroup Bridge 45N - Atmel AT91SAM (dt)";
17 stdout-path = "serial0:115200n8";
26 atheros,board-id = "SD32";
31 compatible = "atmel,sama5d3-rstc";
35 atmel,wakeup-mode = "low";
39 clock-frequency = <32768>;
43 clock-frequency = <12000000>;
48 nand_controller: nand-controller {
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