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/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dphy-hisi-inno-usb2.txt1 Device tree bindings for HiSilicon INNO USB2 PHY
4 - compatible: Should be one of the following strings:
5 "hisilicon,inno-usb2-phy",
6 "hisilicon,hi3798cv200-usb2-phy".
7 - re
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H A Dnvidia,tegra124-xusb-padctl.txt1 Device tree binding for NVIDIA Tegra XUSB pad controller
11 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
12 super-speed USB. Other lanes are for various types of low-speed, full-speed
13 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
14 contains a software-configurable mux that sits between the I/O controller
17 In addition to per-lane configuration, USB 3.0 ports may require additional
18 settings on a per-board basis.
20 Pads will be represented as children of the top-level XUSB pad controller
21 device tree node. Each lane exposed by the pad will be represented by its
23 PHY bindings, as described by the phy-bindings.txt file in this directory.
[all …]
H A Dphy-lantiq-rcu-usb2.txt9 -------------------------------------------------------------------------------
11 - compatible : Should be one of
12 "lantiq,ase-usb2-phy"
13 "lantiq,danube-usb2-phy"
14 "lantiq,xrx100-usb2-phy"
15 "lantiq,xrx200-usb2-phy"
16 "lantiq,xrx300-usb2-phy"
17 - reg : Defines the following sets of registers in the parent
18 syscon device
19 - Offset of the USB PHY configuration register
[all …]
H A Dsamsung-phy.txt2 -------------------------------------------------
5 - compatible : should be one of the listed compatibles:
6 - "samsung,s5pv210-mipi-video-phy"
7 - "samsung,exynos5420-mipi-video-phy"
8 - "samsung,exynos5433-mipi-video-phy"
9 - #phy-cells : from the generic phy bindings, must be 1;
12 - syscon - phandle to the PMU system controller
15 - samsung,pmu-syscon - phandle to the PMU system controller
16 - samsung,disp-sysreg - phandle to the DISP system registers controller
17 - samsung,cam0-sysreg - phandle to the CAM0 system registers controller
[all …]
H A Dti-phy.txt6 - compatible: Should be one of
7 "ti,control-phy-otghs" - if it has otghs_control mailbox register as on OMAP4.
8 "ti,control-phy-usb2" - if it has Power down bit in control_dev_conf register
10 "ti,control-phy-pipe
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H A Dnvidia,tegra124-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
H A Dnvidia,tegra210-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xus
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/freebsd/sys/contrib/device-tree/Bindings/mips/lantiq/
H A Drcu.txt4 This binding describes the RCU (reset controller unit) multifunction device,
5 where each sub-device has its own set of registers.
7 The RCU register range is used for multiple purposes. Mostly one device
14 -------------------------------------------------------------------------------
16 - compatible : The first and second values must be:
17 "lantiq,xrx200-rcu", "simple-mfd", "syscon"
18 - reg : The address and length of the system control registers
21 -------------------------------------------------------------------------------
24 compatible = "lantiq,xrx200-rcu", "simple-mfd", "syscon";
27 big-endian;
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/freebsd/sys/contrib/device-tree/src/arm64/nvidia/
H A Dtegra234-p3768-0000+p3767.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/input/linux-event-codes.h>
4 #include <dt-bindings/input/gpio-keys.h>
6 #include "tegra234-p3767.dtsi"
17 stdout-path = "serial0:115200n8";
22 compatible = "nvidia,tegra194-hsuart";
23 reset-names = "serial";
28 compatible = "nvidia,tegra194-hsuart";
29 reset-names = "serial";
41 vcc-supply = <&vdd_1v8_sys>;
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H A Dtegra234-p3737-0000+p3701-0000.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/linux-event-codes.h>
5 #include <dt-bindings/input/gpio-keys.h>
6 #include <dt-bindings/sound/rt5640.h>
8 #include "tegra234-p3701-0000.dtsi"
12 compatible = "nvidia,p3737-0000+p3701-0000", "nvidia,p3701-0000", "nvidia,tegra234";
21 stdout-path = "serial0:115200n8";
31 dai-format = "i2s";
32 remote-endpoint = <&rt5640_ep>;
[all …]
H A Dtegra186-p3509-0000+p3636-0001.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/linux-event-codes.h>
5 #include <dt-bindings/input/gpio-keys.h>
6 #include <dt-bindings/mfd/max77620.h>
12 compatible = "nvidia,p3509-0000+p3636-0001", "nvidia,tegra186";
30 stdout-path = "serial0:115200n8";
41 phy-reset-gpios = <&gpio_aon TEGRA186_AON_GPIO(AA, 6) GPIO_ACTIVE_LOW>;
42 phy-handle = <&phy>;
43 phy-mode = "rgmii-id";
[all …]
H A Dtegra194-p2972-0000.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/linux-event-codes.h>
5 #include <dt-bindings/input/gpio-keys.h>
7 #include "tegra194-p2888.dtsi"
11 compatible = "nvidia,p2972-0000", "nvidia,tegra194";
24 #address-cells = <1>;
25 #size-cells = <0>;
31 remote-endpoint = <&xbar_i2s1_ep>;
39 dai-format = "i2s";
[all …]
H A Dtegra210-p3450-0000.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/gpio-keys.h>
5 #include <dt-bindings/input/linux-event-codes.h>
6 #include <dt-binding
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/freebsd/sys/contrib/device-tree/Bindings/usb/
H A Dsnps,dwc3.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Felipe Balbi <balbi@kernel.org>
14 be presented as a standalone DT node with an optional vendor-specific
18 - $ref: usb-drd.yaml#
19 - if:
25 - dr_mode
29 $ref: usb-xhci.yaml#
35 - const: snps,dwc3
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H A Ddwc3.txt3 DWC3- USB3 CONTROLLER. Complies to the generic USB binding properties
7 - compatible: must be "snps,dwc3"
8 - reg : Address and length of the register set for the device
9 - interrupts: Interrupts used by the dwc3 controller.
10 - clock-names: list of clock names. Ideally should be "ref",
12 - clocks: list of phandle and clock specifier pairs corresponding to
13 entries in the clock-names property.
16 clocks are optional if the parent node (i.e. glue-layer) is compatible to
18 "cavium,octeon-7130-usb-uctl"
20 "samsung,exynos5250-dwusb3"
[all …]
H A Dnvidia,tegra-xudc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/nvidia,tegra-xudc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra XUSB device mode controller (XUDC)
14 - Nagarjuna Kristam <nkristam@nvidia.com>
15 - JC Kuo <jckuo@nvidia.com>
16 - Thierry Reding <treding@nvidia.com>
21 - enum:
22 - nvidia,tegra210-xudc # For Tegra210
[all …]
H A Dci-hdrc-usb2.txt1 * USB2 ChipIdea USB controller for ci13xxx
4 - compatible: should be one of:
5 "fsl,imx23-usb"
6 "fsl,imx27-usb"
7 "fsl,imx28-usb"
8 "fsl,imx6q-usb"
9 "fsl,imx6sl-usb"
10 "fsl,imx6sx-usb"
11 "fsl,imx6ul-usb"
12 "fsl,imx7d-usb"
[all …]
H A Dmediatek,mtk-xhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/mediatek,mtk-xhci.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 - $ref: usb-xhci.yaml
19 case 2: supports dual-role mode, and the host is based on xHCI driver.
25 - enum:
26 - mediatek,mt2701-xhci
27 - mediatek,mt2712-xhci
[all …]
/freebsd/sys/contrib/device-tree/src/arm/broadcom/
H A Dbcm47094-dlink-dir-890l.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Device tree for D-Link DIR-890L
4 * D-Link calls this board "WRGAC36"
5 * this router has the same looks and form factor as D-Lin
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/freebsd/sys/contrib/device-tree/src/arm/nvidia/
H A Dtegra124-nyan.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/input/input.h>
3 #include <dt-bindings/thermal/thermal.h>
14 stdout-path = "serial0:115200n8";
18 * Note that recent version of the device tree compiler (starting with
20 * missing a unit-address. However, the bootloader on these Chromebook
22 * Adding the unit-address causes the bootloader to create a /memory
24 * turn leads the kernel to believe that the device has 2 GiB of
34 /delete-node/ memory@80000000;
40 vdd-supply = <&vdd_3v3_hdmi>;
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A Dp5040si-post.dtsi2 * P5040 Silicon/SoC Device Tree Source (post include)
4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10000 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10000 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10000 0>;
51 compatible = "fsl,p5040-elbc", "fsl,elbc", "simple-bus";
53 #address-cells = <2>;
[all …]
H A Dt1023si-post.dtsi2 * T1023 Silicon/SoC Device Tree Source (post include)
35 #include <dt-bindings/thermal/thermal.h>
38 compatible = "fsl,bman-fbpr";
39 alloc-ranges = <0 0 0x10000 0>;
43 compatible = "fsl,qman-fqd";
44 alloc-ranges = <0 0 0x10000 0>;
48 compatible = "fsl,qman-pfdr";
49 alloc-ranges = <0 0 0x10000 0>;
53 #address-cells = <2>;
54 #size-cells = <1>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/samsung/
H A Dexynos54xx.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos54xx SoC series common device tree source
5 * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
9 * Device nodes common for Samsung Exynos5410/5420/5422/5800. Specific
28 arm_a7_pmu: arm-a7-pmu {
29 compatible = "arm,cortex-a7-pmu";
30 interrupt-parent = <&gic>;
38 arm_a15_pmu: arm-a15-pmu {
39 compatible = "arm,cortex-a15-pmu";
40 interrupt-parent = <&combiner>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/microchip/
H A Dat91-wb45n.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * at91-wb45n.dtsi - Device Tree file for WB45NBT board
12 model = "Laird Workgroup Bridge 45N - Atmel AT91SAM (dt)";
17 stdout-path = "serial0:115200n8";
26 atheros,board-id = "SD32";
31 compatible = "atmel,sama5d3-rstc";
35 atmel,wakeup-mode = "low";
39 clock-frequency = <32768>;
43 clock-frequency = <12000000>;
48 nand_controller: nand-controller {
[all …]
H A Dat91sam9x5ek.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * at91sam9x5ek.dtsi - Device Tree file for AT91SAM9x5CM Base board
11 model = "Atmel AT91SAM9X5-EK";
16 stdout-path = "serial0:115200n8";
20 compatible = "atmel,sam9x5-wm8731-audio";
24 atmel,audio-routing =
30 atmel,ssc-controller = <&ssc0>;
31 atmel,audio-codec = <&wm8731>;
36 atmel,adc-ts-wires = <4>;
37 atmel,adc-ts-pressure-threshold = <10000>;
[all …]

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