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/linux/Documentation/driver-api/usb/
H A Dwriting_musb_glue_layer.rst2 Writing a MUSB Glue Layer
10 The Linux MUSB subsystem is part of the larger Linux USB subsystem. It
11 provides support for embedded USB Device Controllers (UDC) that do not
15 Instead, these embedded UDC rely on the USB On-the-Go (OTG)
17 reference design used in most cases is the Multipoint USB Highspeed
18 Dual-Role Controller (MUSB HDRC) found in the Mentor Graphics Inventra™
21 As a self-taught exercise I have written an MUSB glue layer for the
22 Ingenic JZ4740 SoC, modelled after the many MUSB glue layers in the
24 ``drivers/usb/musb/jz4740.c``. In this documentation I will walk through the
25 basics of the ``jz4740.c`` glue layer, explaining the different pieces and
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/linux/Documentation/devicetree/bindings/soc/socionext/
H A Dsocionext,uniphier-soc-glue.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-soc-glue.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier SoC-glue logic
10 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
13 SoC-glue logic implemented on Socionext UniPhier SoCs is a collection of
19 - enum:
20 - socionext,uniphier-ld4-soc-glue
21 - socionext,uniphier-pro4-soc-glue
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H A Dsocionext,uniphier-dwc3-glue.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-dwc3-glue.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier SoC DWC3 USB3.0 glue layer
10 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
13 DWC3 USB3.0 glue layer implemented on Socionext UniPhier SoCs is
20 - enum:
21 - socionext,uniphier-pro4-dwc3-glue
22 - socionext,uniphier-pro5-dwc3-glue
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/linux/drivers/usb/dwc2/
H A Dpci.c1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * pci.c - DesignWare HS OTG Controller PCI driver
5 * Copyright (C) 2004-2013 Synopsys, Inc.
20 #include <linux/usb.h>
22 #include <linux/usb/hcd.h>
23 #include <linux/usb/ch11.h>
25 #include <linux/usb/usb_phy_generic.h>
29 static const char dwc2_driver_name[] = "dwc2-pci";
37 * dwc2_pci_remove() - Provides the cleanup entry points for the DWC_otg PCI
44 struct dwc2_pci_glue *glue = pci_get_drvdata(pci); in dwc2_pci_remove() local
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/linux/Documentation/devicetree/bindings/usb/
H A Ddwc3-st.txt1 ST DWC3 glue logic
3 This file documents the parameters for the dwc3-st driver.
4 This driver controls the glue logic used to configure the dwc3 core on
8 - compatible : must be "st,stih407-dwc3"
9 - reg : glue logic base address and USB syscfg ctrl register offset
10 - reg-names : should be "reg-glue" and "syscfg-reg"
11 - st,syscon : should be phandle to system configuration node which
12 encompasses the glue registers
13 - resets : list of phandle and reset specifier pairs. There should be two entries, one
15 - reset-names : list of reset signal names. Names should be "powerdown" and "softreset"
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H A Damlogic,meson-g12a-usb-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/amlogic,meson-g12a-usb-ctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Amlogic Meson G12A DWC3 USB SoC Controller Glue
11 - Neil Armstrong <neil.armstrong@linaro.org>
14 The Amlogic G12A embeds a DWC3 USB IP Core configured for USB2 and USB3
15 in host-only mode, and a DWC2 IP Core configured for USB2 peripheral mode
18 A glue connects the DWC3 core to USB2 PHYs and optionally to an USB3 PHY.
20 One of the USB2 PHYs can be re-routed in peripheral mode to a DWC2 USB IP.
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H A Dam33xx-usb.txt3 - compatible: ti,am33xx-usb
4 - reg: offset and length of the usbss register sets
5 - ti,hwmods : must be "usb_otg_hs"
7 The glue layer contains multiple child nodes. It is required to have
8 at least a control module node, USB node and a PHY node. The second USB
13 - compatible: ti,am335x-usb-ctrl-module
14 - reg: offset and length of the "USB control registers" in the "Control
15 Module" block. A second offset and length for the USB wake up control
17 - reg-names: "phy_ctrl" for the "USB control registers" and "wakeup" for
18 the USB wake up control register.
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H A Domap-usb.txt1 OMAP GLUE AND OTHER OMAP SPECIFIC COMPONENTS
3 OMAP MUSB GLUE
4 - compatible : Should be "ti,omap4-musb" or "ti,omap3-musb"
5 - ti,hwmods : must be "usb_otg_hs"
6 - multipoint : Should be "1" indicating the musb controller supports
7 multipoint. This is a MUSB configuration-specific setting.
8 - num-eps : Specifies the number of endpoints. This is also a
9 MUSB configuration-specific setting. Should be set to "16"
10 - ram-bits : Specifies the ram address size. Should be set to "12"
11 - interface-type : This is a board specific setting to describe the type of
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H A Dmediatek,mtu3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/mediatek,mtu3.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 - $ref: usb-drd.yaml
17 The DRD controller has a glue layer IPPC (IP Port Control), and its host is
23 - enum:
24 - mediatek,mt2712-mtu3
25 - mediatek,mt8173-mtu3
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H A Dmediatek,mtk-xhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/mediatek,mtk-xhci.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 - $ref: usb-xhci.yaml
19 case 2: supports dual-role mode, and the host is based on xHCI driver.
25 - enum:
26 - mediatek,mt2701-xhci
27 - mediatek,mt2712-xhci
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H A Drealtek,rtd-dwc3.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/realtek,rtd-dwc3.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Realtek DWC3 USB SoC Controller Glue
11 - Stanley Chang <stanley_chang@realtek.com>
14 The Realtek DHC SoC embeds a DWC3 USB IP Core configured for USB 2.0
15 and USB 3.0 in host or dual-role mode.
20 - enum:
21 - realtek,rtd1295-dwc3
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/linux/drivers/usb/chipidea/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
12 Say Y here if your system has a dual role high speed USB
14 Dual-role switch (ID, OTG FSM, sysfs), Host-only, and
15 Peripheral-only.
37 tristate "Enable PCI glue driver" if EXPERT
43 tristate "Enable MSM hsusb glue driver" if EXPERT
47 tristate "Enable NPCM hsusb glue driver" if EXPERT
51 tristate "Enable i.MX USB glue driver" if EXPERT
56 tristate "Enable generic USB2 glue driver" if EXPERT
60 tristate "Enable Tegra USB glue driver" if EXPERT
/linux/Documentation/driver-api/media/drivers/
H A Dpvrusb2.rst1 .. SPDX-License-Identifier: GPL-2.0
9 ----------
11 This driver is intended for the "Hauppauge WinTV PVR USB 2.0", which
12 is a USB 2.0 hosted TV Tuner. This driver is a work in progress.
13 Its history started with the reverse-engineering effort by Björn
29 1. Low level wire-protocol implementation with the device.
38 tear-down, arbitration, and interaction with high level
42 5. High level interfaces which glue the driver to various published
61 --------
70 --------------------------------------
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/linux/drivers/usb/dwc3/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
5 depends on (USB || USB_GADGET) && HAS_DMA
11 USB controller based on the DesignWare USB3 IP Core.
27 default USB_DWC3_DUAL_ROLE if (USB && USB_GADGET)
28 default USB_DWC3_HOST if (USB && !USB_GADGET)
29 default USB_DWC3_GADGET if (!USB && USB_GADGET)
33 depends on USB=y || USB=USB_DWC3
47 depends on ((USB=y || USB=USB_DWC3) && (USB_GADGET=y || USB_GADGET=USB_DWC3))
54 comment "Platform Glue Driver Support"
78 tristate "PCIe-based Platforms"
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H A Ddwc3-haps.c1 // SPDX-License-Identifier: GPL-2.0
3 * dwc3-haps.c - Synopsys HAPS PCI Specific glue layer
19 * struct dwc3_haps - Driver private structure
30 PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"),
44 struct device *dev = &pci->dev; in dwc3_haps_probe()
51 return -ENODEV; in dwc3_haps_probe()
58 return -ENOMEM; in dwc3_haps_probe()
60 dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO); in dwc3_haps_probe()
61 if (!dwc->dwc3) in dwc3_haps_probe()
62 return -ENOMEM; in dwc3_haps_probe()
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H A Ddwc3-imx8mp.c1 // SPDX-License-Identifier: GPL-2.0
3 * dwc3-imx8mp.c - NXP imx8mp Specific Glue layer
21 /* USB wakeup registers */
41 /* USB glue registers */
45 #define USB_CTRL0_PORTPWR_EN BIT(12) /* 1 - PPC enabled (default) */
46 #define USB_CTRL0_USB3_FIXED BIT(22) /* 1 - USB3 permanent attached */
47 #define USB_CTRL0_USB2_FIXED BIT(23) /* 1 - USB2 permanent attached */
49 #define USB_CTRL1_OC_POLARITY BIT(16) /* 0 - HIGH / 1 - LOW */
50 #define USB_CTRL1_PWR_POLARITY BIT(17) /* 0 - HIGH / 1 - LOW */
66 struct device *dev = dwc3_imx->dev; in imx8mp_configure_glue()
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/linux/arch/arm/boot/dts/socionext/
H A Duniphier-pro4.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/gpio/uniphier-gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 compatible = "socionext,uniphier-pro4";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "arm,cortex-a9";
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/linux/Documentation/devicetree/bindings/phy/
H A Dkeystone-usb-phy.txt1 TI Keystone USB PHY
4 - compatible: should be "ti,keystone-usbphy".
5 - #address-cells, #size-cells : should be '1' if the device has sub-nodes
7 - reg : Address and length of the usb phy control register set.
9 The main purpose of this PHY driver is to enable the USB PHY reference clock
12 phy node in the USB Glue layer driver node.
15 compatible = "ti,keystone-usbphy";
16 #address-cells = <1>;
17 #size-cells = <1>;
/linux/drivers/usb/host/
H A Dohci-sa1111.c1 // SPDX-License-Identifier: GPL-1.0+
3 * OHCI HCD (Host Controller Driver) for USB.
6 * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
7 * (C) Copyright 2002 Hewlett-Packard Company
9 * SA1111 Bus Glue
17 #include <asm/mach-types.h>
21 #error "This file is SA-1111 bus glue. CONFIG_SA1111 must be defined."
46 unsigned long status = readl_relaxed(hcd->regs + USB_STATUS);
80 .product_desc = "SA-1111 OHCI",
126 dev_dbg(&dev->dev, "starting SA-1111 OHCI USB Controller\n"); in sa1111_start_hc()
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H A Dehci-pci.c1 // SPDX-License-Identifier: GPL-2.0+
3 * EHCI HCD (Host Controller Driver) PCI Bus Glue.
5 * Copyright (c) 2000-2004 by David Brownell
11 #include <linux/usb.h>
12 #include <linux/usb/hcd.h>
15 #include "pci-quirks.h"
19 static const char hcd_name[] = "ehci-pci";
27 /*-------------------------------------------------------------------------*/
31 return pdev->vendor == PCI_VENDOR_ID_INTEL && in is_intel_quark_x1000()
32 pdev->device == PCI_DEVICE_ID_INTEL_QUARK_X1000_SOC; in is_intel_quark_x1000()
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/linux/drivers/dma/ti/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
12 is currently used by the USB driver on AM335x and DA8xx platforms.
27 tristate "Texas Instruments sDMA (omap-dma) support"
51 tristate "Texas Instruments UDMA Glue layer for non DMAengine users"
55 Say y here to support the K3 NAVSS DMA glue interface
/linux/drivers/usb/storage/
H A Dscsiglue.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Driver for USB Mass Storage compliant devices
4 * SCSI Connecting Glue Header File
7 * (c) 1999, 2000 Matthew Dharm (mdharm-usb@one-eyed-alien.net)
9 * This driver is based on the 'USB Mass Storage Class' document. This
13 * similar to commands in the SCSI-II and ATAPI specifications.
16 * exhibits class-specific exemptions from the USB specification.
/linux/drivers/usb/mtu3/
H A Dmtu3.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * mtu3.h - MediaTek USB3 DRD header
22 #include <linux/usb.h>
23 #include <linux/usb/ch9.h>
24 #include <linux/usb/gadget.h>
25 #include <linux/usb/otg.h>
26 #include <linux/usb/role.h>
35 #define MU3D_EP_TXCR0(epnum) (U3D_TX1CSR0 + (((epnum) - 1) * 0x10))
36 #define MU3D_EP_TXCR1(epnum) (U3D_TX1CSR1 + (((epnum) - 1) * 0x10))
37 #define MU3D_EP_TXCR2(epnum) (U3D_TX1CSR2 + (((epnum) - 1) * 0x10))
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/linux/Documentation/devicetree/bindings/mips/cavium/
H A Ductl.txt1 * UCTL USB controller glue
4 - compatible: "cavium,octeon-6335-uctl"
8 - reg: The base address of the UCTL register bank.
10 - #address-cells: Must be <2>.
12 - #size-cells: Must be <2>.
14 - ranges: Empty to signify direct mapping of the children.
16 - refclk-frequency: A single cell containing the reference clock
19 - refclk-type: A string describing the reference clock connection
24 compatible = "cavium,octeon-6335-uctl";
27 #address-cells = <2>;
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/linux/drivers/input/
H A Djoydev.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 1999-2002 Vojtech Pavlik
47 struct JS_DATA_SAVE_TYPE glue; member
50 __u16 keymap[KEY_MAX - BTN_MISC + 1];
51 __u16 keypam[KEY_MAX - BTN_MISC + 1];
70 switch (corr->type) { in joydev_correct()
76 value = value > corr->coef[0] ? (value < corr->coef[1] ? 0 : in joydev_correct()
77 ((corr->coef[3] * (value - corr->coef[1])) >> 14)) : in joydev_correct()
78 ((corr->coef[2] * (value - corr->coef[0])) >> 14); in joydev_correct()
85 return clamp(value, -32767, 32767); in joydev_correct()
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